Commit graph

6 commits

Author SHA1 Message Date
Piotr Wojnarowski 2f5ac45e53 dts: bindings: interrupt-controller: GIC: Allow specifying version in DT
Currently, only the presence of a GIC is reflected in the device tree,
and its version must be set separately in each SoC's Kconfig.
This patch adds separate bindings for each GIC version whose presence
in the device tree automatically enables the corresponding Kconfig symbol.

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Rodrigo Cataldo 04f519a7c3 drivers: interrupt_controller: imply the need for dynamic memory in ITS
The implementation of GIC v3 ITS uses k_aligned_malloc(), which will
only work if dynamic memory is available (system heap). Tell the user
that a dynamic memory pool is required.

The amount of memory will depend on registers probed during runtime.

Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
2023-04-07 13:26:01 +02:00
Jaxson Han 2866e2a4cc drivers: gicv3: Introduce aff0 matching config for rdist
Some platforms only use aff0 to match mpdir and GICR.aff. Introduce
GIC_V3_RDIST_MATCHING_AFF0_ONLY to set the matching method only using
aff0. With this config enabled, the matching function will find the
target redistributor by comparing the aff0 only.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2022-09-21 15:21:29 +02:00
Neil Armstrong a737999b5b interrupt_controller: gicv3: add Interrupt Translation Service support
This implements support for the optional Interrupt Translation Service
(ITS) module of the GICv3 Interrupt Controller.

The current implementation is designed for MSI/MSI-X interrupt delivery
in mind.
The gicv3 driver calls each ITS INVALL command when LPI interrupts are
enabled/disabled.
A simple atomic integer is used to allocate unique LPI INTIDs to ITS
users.
CPUs numbers are directly mapped as ICIDs into the Collections Table.

As a limitation it doesn't support indirect Device table to simplify
implementation but may use a large amount of memory.

INV, DISCARD, MOVI and MOVALL commands are not implemented.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00
Jaxson Han 36006ed1ba drivers: gicv3: GIC with single secure mode
The Cortex-R 64-bit processor only supports GIC with single
security mode

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
2021-04-13 07:47:44 -04:00
Stephanos Ioannidis 11d0f0a294 drivers: interrupt_controller: Refactor GIC configurations
The current GIC configuration scheme is designed to support only one
specific type and version of GIC (i.e. GIC-400 that implements the
GICv2 interface).

This commit adds a set of GIC version configuration symbols that can
be selected by the SoC configuration to specify which version of GIC
interface is implemented in the SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-19 11:05:27 -05:00