Commit graph

63 commits

Author SHA1 Message Date
Francois Ramu
f106465741 drivers: flash: ospi driver erase command on 24bits in SPI mode
When configuring the octo-flash in SPI/STR mode, the address size
must be on 24bits (and not on 32bits).
Despite the dev_data->address_width which is always seen as 4, the
erase command must reduce the AddressSize for this transfer mode.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-08-25 21:05:27 +00:00
Henrik Brix Andersen
c1a35b7b39 drivers: flash: check if clock device is ready before accessing
Add check for device_is_ready() before accessing clock control devices.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-08-09 17:16:16 +02:00
Francois Ramu
0852cf9eee drivers: flash: ospi for stm32 mcu
Fixes command configuration to have samples/drivers/spi_flash
passed on stm32l562 and stm32u585 disco kits.
In OctoSPI STR/DTR and SPI/STR modes

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-08-09 15:59:18 +01:00
Erwan Gouriou
1ef9e9eb9b include: drivers: stm32 clock_control: Replace OPT by DOMAIN
In the continuation of the previous commit, replace _OPT_ by _DOMAIN_
in macros relating to this feature.
hen, adapt drivers and tests to this new wording.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-08-08 14:17:07 +02:00
Francois Ramu
b165f10795 drivers: flash: octospi drivers for stm32h7 serie
With the introduction of the OSPI NOR flash controller
the stm32H7 serie requires the HAL MDMA in anycase.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-27 18:46:25 +02:00
Francois Ramu
764dbbf355 drivers: flash: stm32 ospi driver configures peripheral clock
The clock of the octospi peripheral is directly defined
by the DTS and configured by the clock_control_on function.
No specific stm32cube function is required then.
The clock control is taking this clock source to calculate
the clock rate.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-04 15:18:50 +02:00
Francois Ramu
80dd57a49d drivers: flash: stm32 ospi driver align erase on sector size
When erasing the flash, the size to erase must be
compared to a multiple of SECTOR_SIZE.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-06-29 10:30:04 +02:00
Georgij Cernysiov
bf974902bf drivers: flash: stm32: ospi: writing single, dual and quad modes
Support writing to NOR-Flash over OSPI using
the following modes:

* 1-1-1
* 1-1-4
* 1-4-4

Supports 4-Byte opcodes conversion for write opcodes.

Allows users to set what write/program opcode is used
in the DTS (not for OPI mode).
Will use some default PP opcodes based on the mode.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-06-16 10:29:15 +02:00
Georgij Cernysiov
f278db7071 drivers: flash: stm32: ospi: support SFDP quad enable requirements
Adds support for `quad enable requirements` DTS property.

Parses SFDP:BFP DW15 (QER related) and uses it (if available),
it bypasses the DTS property.

Automatically enables quad mode (if required).

Supports every DW15 QER modes.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-06-16 10:29:15 +02:00
Georgij Cernysiov
871ded0e65 drivers: flash: stm32: ospi: read/erase single, dual and quad modes
Adds support to read and erase NOR-Flash over OSPI using
the following modes:

* 1-1-2
* 1-2-2
* 1-1-4
* 1-4-4

Supports 4-Byte opcodes conversion and gets address width
from the SFDP:BFP.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-06-16 10:29:15 +02:00
Georgij Cernysiov
e8dece902f drivers: flash: stm32_ospi: fix includes
Adds `zephyr/...` prefix to `toolchain.h` include.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-05-25 11:13:40 +09:00
Francois Ramu
084dc3f0dd drivers: flash: ospi factorized for stm32 devices
Simplifies the driver and Gives a generic function to prepare the Regular
commands for each instruction.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-05-12 14:56:25 -05:00
Francois Ramu
16754378fb drivers: flash : introduce a new driver for the OCTOSPI
This is the stm32 octospi driver based on the exisitng quadspi
 for stm32 devices and source code from the STM32Cube.
This drivers initialized the peripheral and the NOR memory
in SPI or OctoSPI mode with STR or DTR data Transfer rates.
The NOR-flash can provide the SDFP table directly (if supported)
or through the DeviceTree.
 Limitation: no DMA transfer.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-05-12 14:56:25 -05:00