Add the loop to wait until the stream is really disable after disabling
and also cleared the TCIF flag.
This is a specifity of the dma of type V1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
To support the repeated start/stop, the stm32 dma driver is
returning 0 if the channel is already started/stopped.
This is not done at the dmamux level if any.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This function is responsible for checking if combination of msize,
mburst and FIFO level is allowed. Possible combinations can be found in
ST documentation, eg. Table 36. FIFO threshold configurations, RM0402
9.3.13 FIFO chapter.
Previously there was no 'break' or '__fallthrough' in msize switch which
caused compilation errors. Since we are confirming that combination is
correct, 'break' statements should be used.
Besides of introducing missing 'break' statements, this patch moves
'return false' from switch to the end of the function. This makes code
shorter and easier to understand, because we have only correct
combinations.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the missing parts for adding support
to stm32h7 dma driver.
The fix is to make dmamux driver work with
dma v1 driver.
Signed-off-by: Shlomi Vaknin <shlomi.39sd@gmail.com>
When checking for IRQ flags, we should also check
for IRQ status (IsEnabled ?).
If this is not done we can end up in Half Transfer
interrupt processing while it is not enabled.
Additionaly always use the id translation function
in LL API calls.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The stm32_dma_disable_stream first checked if the stream was
disabled and if so returned OK. If it wasn't disabled it
tried to disable it and returned -EAGAIN.
The function is used in loops that try to disable the stream
by calling this function and if it fails wait for 1ms and
retry.
Becuase this function the first time (if the stream wasn't
disabled already) fails there is always a 1 ms delay. For
the SPI driver, that has a RX and TX stream, this means
a 2ms delay between the last data and CS going high.
By first trying to disable the stream and than checking
if it succeded most of the time the first call disables
the stream and the 1ms delay isn't needed.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Convert global conversion tables for id-to-stream and slot-to-channel
to functions that use local const static conversion tables.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
- Remove the need for kmalloc
- On hardware that supports it use 1 IRQ handler per stream to
determine the stream ID, so the ISR does not have to loop
over all ID's to see which one is active. On hardware (like
STM32L0 and STM32F0) where up to 7 streams share 3 IRQ's use
the loop to check which stream is active.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
define the irq handler in case of DMA V1 or V2,
for the stm32x soc series
with DMA V1 raise Fifo Error if enabled
with V2, handle the Global Interrupt
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The DMA driver of stm32 used to use `stm32_dma_enable_fifo()`,
which is located in dma_stm32_v1.c to set DMDIS bit, enable
interrupt generation and set FIFO threshold. Now since FIFO
threshold is initialized with `stm32_dma_get_fifo_threshold()`
and interrupt generation is also configured in dma_stm32.c, this
function will only have one job, to configure FIFO mode.
We can add FIFO mode operation in dma_stm32.c directly and
remove it from dma_stm32_v1.c.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
