This commit introduces a driver for NXP's eDMA IP.
The main reasons for introducing a new driver are the following:
1) The HAL EDMA wrappers don't support well different
eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new
revision had to be introduced, thus requiring a new Zephyr
driver.
2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP
don't use the DMAMUX IP (instead, channel MUX-ing is performed
through an eDMA register in the case of i.MX93).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add an emulated DMA driver. Emulation drivers are great to have
for each driver API for multiple reasons:
- providing an ideal / model driver for reference
- potential for configurable backend support
- seamless integration with device tree
- multi-instance, etc, for all supported boards
- fast regression testing of app and library code
Since many other drivers and lbraries depend on DMA, this might
help us to increase test coverage.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
This commit introduces the SOF host DMA driver.
This driver is used by NXP platforms in the context of
SOF's host component to copy data from the host memory
to the firmware (local) memory. This is possible because
NXP platforms can access the host memory directly w/o
an actual DMA engine.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Introduce SMARTDMA dma driver. The SMARTDMA is a peripheral present on
some NXP SOCs, which implements a programmable DMA engine. The DMA
engine does not use channels, but rather provides a series of API
functions implemented by the firmware provided with MCUX SDK.
These API functions can be selected by the dma_config slot parameter. A
custom API is also provided to allow the user to install an alternate
firmware into the SMARTDMA.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".
Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Adds an initial driver for HDA streams on cAVS. A common code base is
provided for all HDA streams while the drivers are identified
differently as they have small behavior differences.
Uses dma_status to describe the positions for read/write. Uses dma_reload
to inform when to move the read/write positions. This closely follows
how HDA is being used in SoF
Simple test case is provided for both drivers.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel's adsp needs to set, at a minimum, a clocking bit before the driver
can initialize the designware dma controller. In many ways it is the
designware dmac IP but with additional registers and functionality added
on top of it. So the code structure here follows how the hardware
appears to be designed, layered on top of the designware driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Refactors all of the DMA drivers to use a shared driver class
initialization priority configuration, CONFIG_DMA_INIT_PRIORITY, to
allow configuring DMA drivers separately from other devices. This is
similar to other driver classes like I2C and SPI.
Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_DEFAULT or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
All dma drivers are devicetree based now so we can remove the last
bits of Kconfig associated with the old driver style.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add PAX[PCIE<->AXI] DMA driver which supports DMA
transfers between host and target memory over PCIe link.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add PL330 dma driver support, this driver
- supports 32 bit memory to memory operation
- supports 36 bit memory to memory operation
under a config flag DMA_64BIT
- supports secure channel
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Add 64bit source_address/dest_address fields support.
This is needed in situation where DMA controller is capable
of handling more than 32bit source and destination addresses.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
tested on mimxrt1060_evt
MEMORY_NOCACHE is needed
test on frdmk64f
special test slot need configure with
CONFIG_DMA_TEST_SLOT_START
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
There is no such thing as CAVS DMA IP block, the DMA IP block found on
CAVS based chips is made with DesignWare one.
This will help to centralize DW based DMA device into one driver.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit adds driver support for DMA on f0/f1/f2/f3/f4/l0/l4
series stm32.
Notice due to some bugs, this is currently not working with f7.
There are two kinds of IP blocks are used across these stm32, one is the
one that has been used on F2/F4/F7 series, and the other one is the one
that has been used on F0/F1/F3/L0/L4 series.
Memory to memory transfer is only supported on the second DMA on
F2/F4 with 'st,mem2mem' to be declared in dts.
This driver depends on k_malloc to allocate memory for stream instances,
so CONFIG_HEAP_MEM_POOL_SIZE must be big enough to hold them.
Common parts of the driver are in dma_stm32.c and SoC related parts are
implemented in dma_stm32_v*.c.
This driver has been tested on multiple nucleo boards, including
NUCLEO_F091RC/F103RB/F207ZG/F302R8/F401RE/L073RZ/L476RG with the
loop_transfer and chan_blen_transfer test cases.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Use this short header style in all Kconfig files:
# <description>
# <copyright>
# <license>
...
Also change all <description>s from
# Kconfig[.extension] - Foo-related options
to just
# Foo-related options
It's clear enough that it's about Kconfig.
The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)
git ls-files '*Kconfig*' | \
xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Added in commit bb36c0af86 ("dma: Add possibility for up to 3 DMA
Controllers") in February 2017, then never used.
Found with a script.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Remove DCACHE_WRITEBACK Kconfig variable definition in Intel S1000
DMA driver. Remove the variable from default configuration as well.
Cache configuration is fixed and the cache operation routines
internally take appropriate action based on the cache configuration.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Consistently use
config FOO
bool/int/hex/string "Prompt text"
instead of
config FOO
bool/int/hex/string
prompt "Prompt text"
(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).
The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.
Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though, and is
inconsistent.
This will make the auto-generated Kconfig documentation have "No
defaults. Implicitly defaults to n." as well, which is clearer than
'default n if ...'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Add dma driver for Nios-II Modular Scatter-Gather DMA soft IP.
This driver relies upon the Altera HAL msgdma driver for all
the dma core register programming and interrupt handling.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.
This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.
Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Fix misspellings in Kconfig help text and made spelling of
RX and TX consistent (from reviewer comments)
Change-Id: Ie9d4c3863cd210e7a17b50a85a7e64156b6bf3d7
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Some controllers contain channels with-in channels, or in the case
of the STM32 DMA controller channels within streams. Channels
will vary depending on application, so these need to be provided
on a use-case bases.
Change-Id: I4f5fe3ec5817583b95dc7f059b5dc57f937523c4
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Currently only 1 is allowed. While we're at it, let's generify the
existing entries, since they could be used by all controllers, not
just QMSI.
Change-Id: Iec5d195fff239931b21a7584eb4b642b40f95be5
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This driver currently only handles memory-to-memory transfers.
TODO: Add support for all types of transfers.
Change-Id: Ic9787dcca919a58fb11b48c9f6b6b371db88c3ea
Origin: Original
Maintained-by: Zephyr
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Michael Hope
