The devicetree tells this driver which system power states stop its
output, and nothing read it. A consumer holding a runtime reference on
an instance whose node lists zephyr,disabling-power-states could still
have the policy pick one of those states and lose the voltage it asked
for, with no error anywhere.
Take the per-device policy constraint for as long as the output is on:
when a value is first written, again when a resume restores it, and
released in SUSPEND, which under runtime device PM is where the last
consumer reference goes away. A re-run of dac_channel_setup() releases
it too, because DAC_Init() leaves GCR[DACEN] clear.
That pins the constraint to the one fact the driver does know -- the
output buffer is on -- rather than to the length of an API call, which
for a DAC is not the length of anything. The consumer keeps owning the
output's lifetime through its runtime reference, and no longer has to
name the states that would break it.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
A call that lands on a suspended instance writes GCR[DACEN] and DATA
and returns success while the analog output buffer stays off. On a
device the core has turned off the write goes into a register block
that has lost its contents, and the driver's cached value then
disagrees with the hardware until the next resume replays it.
Check the device state at the point where each API call is about to
touch the registers and return -EBUSY instead. Argument validation is
left ahead of the check so that a bad channel or resolution still
reports -ENOTSUP regardless of the power state.
With CONFIG_PM_DEVICE=n, pm_device_state_get() reports the device as
active, so this costs nothing when device PM is not in use.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Suspend-to-RAM resume re-runs SystemInit() and
board_early_init_hook(), so the clock and the analog power request
come back, but it does not re-run driver init: GCR and DATA stay at
their reset values while the driver still reports a configured DAC,
and the next dac_write_value() writes a value the block cannot convert
with the settings the devicetree asked for.
TURN_ON is the only action that runs after the block lost power, so
the rebuild goes there. Limit it to an instance the application has
already set up, so a DAC nobody has touched keeps the reset state it
had rather than having a configuration written into it on the way
back. The rebuild leaves GCR[DACEN] clear, which is the state the core
records for the device once TURN_ON returns; RESUME is what puts the
output back, and the core does not call it at all when runtime PM will
take over.
TURN_OFF has nothing to do: the core suspends a device before it turns
it off, so the output buffer is already off, and this driver holds no
clock or regulator reference to release.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Route init through pm_device_driver_init() and add a PM callback that
stops and restarts the DAC.
SUSPEND clears GCR[DACEN] and applies the sleep pin state. Clearing
DACEN switches the analog output buffer off; gating the DAC clock
would only freeze the buffer at its current level.
RESUME applies the default pin state and replays the last value
written, so a consumer that was holding the output across a
transition gets it back without calling dac_channel_setup() again. An
instance whose value was never written stays disabled instead of
driving a pin at 0 V. The two new data fields track that value, which
cannot be read back out of a register block whose clock may have been
gated.
Applying the default pin state moves from init to RESUME because it
is now reachable more than once. Init still applies it:
pm_device_driver_init() tolerates -ENOTSUP from TURN_ON, which this
driver does not implement, and then calls RESUME.
The callback is compiled unconditionally. With CONFIG_PM_DEVICE=n the
sequence is the same TURN_ON-then-RESUME, which on a DAC that has not
been set up yet applies the pins and touches nothing else -- the same
register sequence as before this change -- and
PM_DEVICE_DT_INST_DEFINE() and PM_DEVICE_DT_INST_GET() are no-ops
there. Both are parameterized by the instance index, so a
two-instance build is not a redefinition error.
With CONFIG_PM_DEVICE_RUNTIME the driver takes no runtime reference of
its own: the consumer holds one for as long as it wants the output.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
channel_setup() is the only place that writes the devicetree configuration
into the register block, which makes it the only place that can rebuild a
block whose registers were reset. Move those writes into
mcux_lpdac_configure() so a second caller can be added without duplicating
them.
No behavioural change. The DAC_Enable(false) that followed DAC_Init() is
dropped rather than moved: DAC_Init() assigns GCR in full, so DACEN is
already clear when it returns.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The binding includes pinctrl-device.yaml and every in-tree board that
enables a 12-bit DAC node hands it a pinctrl-0 group, but the driver never
called pinctrl_apply_state(), so those groups had no effect. The DAC output
worked anyway on the affected boards because PORT PCR[MUX] selects the
analog function at reset, which is what the pinmux groups also ask for.
The driver now uses the pinctrl API, so select PINCTRL, which the Kconfig
entry for the other in-tree DAC on these parts already does.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
Some notices did not have SPDX tags.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Wheeler Keith (ES ICW SW MTP EE) <Keith.Wheeler@infineon.com>
Use controller/peripheral and SDO/SDI terminology in the remaining
SPI-using drivers (audio, auxdisplay, bluetooth HCI, dac, eeprom,
ethernet, flash, fpga, gpio, haptics, hdlc_rcp_if, ieee802154,
input, led, led_strip, lora, mfd, misc, mux, rtc, sdhc, stepper,
video, watchdog, wifi) and the ec_host_cmd SPI STM32 backend,
following coding guideline rule A.2: switch to
SPI_OP_MODE_CONTROLLER/PERIPHERAL and SPI_SDO_OVERRUN_DT, rename
Zephyr-owned identifiers (the HCI SPI header buffers, the winc1500
bus wrapper transfer parameters), and update comments, log messages
and Kconfig help prose.
Vendor and out-of-scope identifiers keep their names: STM32
LL_SPI_MODE_SLAVE in the ec_host_cmd backend, the ATWINC1500 SDK I2C
SLAVE_ADDRESS definition, and the I2S codec clock-role variable in
tlv320aic26.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
The REUSE tool then folds the literal "<text>" into the holder name
and drops the second line from the SBOM.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Add a DAC driver for the 10-bit, 30Msps DAC inside the PSC3 series'
HPPASS CSG. Each instance represents a single DAC inside a CSG slice.
This driver implements the Zephyr DAC API in direct-write only mode (no
LUT or slope generation). The driver handles DAC configuration and
output settings, as well as interrupt handling for the DAC interrupt.
The driver provides for deglitch properties (see TRM reference for
details) and sets an (optional) initial value for the DAC output.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
The init sanity check on the DAC_RES status field logged an error but
returned ret, which the preceding successful status read had set to
0, so a failed identity check still reported successful init. Return
-EIO.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The syscall handler functions forward parameters with identical casts
that are redundant since the variables already have those types. Drop
the casts to let the compiler type-check the arguments unobstructed.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Enable the following G1 DAC Kconfig options by default for
Microchip SAM D5x/E5x devices:
- DAC_MCHP_G1_REFRESH
- DAC_MCHP_G1_EXTERNAL_FILTER
- DAC_MCHP_G1_OVERSAMPLING_RATIO
These Kconfig symbols were introduced during the addition
of DAC driver support for PIC32CX SG family devices, but
the default enablement for SAM D5x/E5x devices was missed.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
The DACC_MR_ONE bit has to be set to one in the DAC driver
but it only applies to SAM4S and SAM4E.
SAM3S and SAM3X, SAM3A do on have this bit.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Implement a common function to validate a DAC channel ID (and translate
it to an "index" value, ultimately used to obtain the LL channel value).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The number of channels supported by an instance is a fixed value so it
can be saved in the instance configuration instead of the instance data.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Update AD5529R_PRODUCT_ID from 0x4140 to 0x414A to match the
released datasheet (Rev. 0) PRODUCT_ID_L register reset value.
Signed-off-by: Radu Ciobanu <Radu-rares.Ciobanu@analog.com>
Use min/max DT properties for ADC nchannels DT properties to factorize
documentation and build time check of the property values against its
valid range.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Corrected PSE84 autanalog DAC index calculation. The DAC index is
contiguous and starts from dac0 instance. The previous implementation
was depending on the DT_NODE_CHILD_IDX, which returns the position
among all autanalog siblings (CTB, PTC, DAC, SAR, PRB). Therefore
it was returning an incorrect DAC index.
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The TI DAC43608 has 8 bit resolution, the DAC53608 has 10 bit
resolution. According to the datasheet from Texax Instruments,
the MSB of DACn_DATA must be left aligned.
This fix aligns the data correctly, allowing the DAC value to
be set to 100% and not only 25% max for the DAC43608.
Signed-off-by: Stephan Gatzka <stephan.gatzka@gmail.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Select the internal 4.096V reference during init. The REF_SEL register
defaults to external, causing 0V output when no external reference is
connected.
Signed-off-by: Radu Ciobanu <Radu-rares.Ciobanu@analog.com>
Add DAC driver for the Analog Devices AD5529R 16-channel, 16-bit
voltage output DAC. The driver supports multiple output voltage
ranges, SPI communication, and optional reset/LDAC/clear GPIOs.
Signed-off-by: Robert Budai <robert.budai@analog.com>
Co-authored-by: Radu Ciobanu <raduciobanu096@gmail.com>
Add support for the DAC module on TI’s MSPM0 G-Series MCUs. The DAC
supports 8-bit and 12-bit resolution.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
For use in tests where the existing "vnd,dac" driver doesn't work as it
returns error codes for all API functions. The approach is mimicked from
the adc-emul driver.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add shared code in 'dac_dacx311.c' and configuration files.
Support power mode bits via configuration.
Signed-off-by: Andreas Wolf <awolf002@gmail.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Most drivers for Series 2 depend on clock control, but didn't
declare it. Enable clock control by default for Series 2 SoCs.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Use STM32_CLOCK_INFO(), STM32_DT_INST_CLOCK_INFO(),
STM32_CLOCK_INFO_BY_NAME() and STM32_DT_INST_CLOCK_INFO_BY_NAME()
helper macros in STM32 drivers.
Using these macros ensure the clock division factor is properly
populated according to DT information. Prior these changes some
drivers only got the bus and bits position information and missed
the clock division information which is fine only when this division
factor information is 0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The Analog Device AD5601, AD5611, and AD5621 devices are 8, 10 and 12
bits DAC respectively.
These devices use a 16 bits SPI communication protocol.
The 2 first bit encode the low power mode (this driver do not use the
low power mode, it always run in the 'normal' mode).
The next 14 bits contain the left aligned value. The 2, 4, or 6
remaining bits (depending on the resolution) are set to 0.
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
The SAMC21 has a different revision of the DAC peripheral.
This change adds an ifdef to handle the changed SYNCBUSY register.
Signed-off-by: Stefan Giroux <stefan.g@feniex.com>
Added support for selecting channels A, B, both together, and all channels
on the AD5686 DAC driver. This improves flexibility for multi-channel
DAC applications.
Signed-off-by: Aditya Ganesh <adga5133@colorado.edu>
This implements the DAC driver for silabs VDAC peripherals
using the silabs,vdac compatible binding.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Added driver and binding file for samd5x dac peripheral, the already
implemented dac_sam0.c lacks the configuration registers for this
microcontroller family and is fixed to only have one dac channel output,
also, the code gets too bulky when adding the samd5x dac configuration
using preprocessor directives that’s why I moved the implementation to its
own file.
Added dac to the supported list of same54_xpro.yaml, fixed Kconfig.samd5x
help spacing, added board defines to test_dac.c and test it out with
twister script on board.
Signed-off-by: Rafael Aldo Hernández Luna <aldo.hernandez@daikincomfort.com>
