Added pm_action suspend/resume/turn_on routine for Counter
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
counter_get_frequency() is allowed to be called from a counter alarm or
top-value callback, which runs in the counter ISR. The Infineon TCPWM
counter driver implemented get_freq() by querying the peripheral clock
tree on every call via the PDL (Cy_SysClk_PeriPclkGetFrequency ->
Cy_SysClk_ClkHfGetFrequency).
On non-secure builds (TrustZone-M with TF-M) that PDL clock query is
serviced by the secure world through a PSA / secure-request round-trip.
Such calls are not permitted from interrupt context, so invoking
counter_ticks_to_us() / counter_get_frequency() from an alarm callback
made the secure request fail and the PDL assertion fault the core,
hanging the application. In thread context the same query works, and
secure builds read the clock registers directly, so the failure was
specific to the non-secure interrupt path.
The counter input clock is fixed once the peripheral divider is assigned
at init. Cache the frequency during device init (thread context) and
return the cached value from get_freq(). This makes
counter_get_frequency() safe to call from the counter ISR and also
avoids a clock-tree walk on every call.
Run the driver init at POST_KERNEL rather than PRE_KERNEL_1: on the CM55
the same clock query is relayed to the secure world over IPC and blocks
on a semaphore, which is not available before the kernel is up.
POST_KERNEL populates the cache once the kernel and the relay are ready,
and still before any application arms an alarm, so the cached value is
always valid when get_freq() runs from an ISR. Also fail init with -EIO
if the frequency reads back as 0.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
ifx_tcpwm_counter_set_top_value() previously updated only the software
cache (data->value) and never reset the hardware counter register.
After counter_set_top_value() reduced the period (PERIOD register), the
TCPWM CNT register kept its old value. If that value was greater than
the new period, the counter had to wrap the full 16-bit (or 32-bit)
range before terminal count, instead of one new period's worth of
ticks.
This caused tests/drivers/counter/counter_basic_api
test_set_top_value_with_alarm to fail on Infineon TCPWM-based boards:
the test computes its timeout assuming the alarm fires within a few
new periods, but the first turnaround took several seconds (e.g. ~6 s
on a 16-bit counter clocked at 10 kHz).
Reset the hardware counter to 0 after writing the new period. When
COUNTER_TOP_CFG_DONT_RESET is set, return -ETIME if the current value
is already past the new ticks (matching the counter API contract);
also reset to 0 in that case when COUNTER_TOP_CFG_RESET_WHEN_LATE is
set.
Verified on kit_pse84_eval (m33+m55), kit_pse84_ai (m33+m55) and
cyw920829m2evk_02: all counter_basic_api subtests pass.
Assisted-by: GitHub Copilot (Claude)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Updates the Infineon Counter and PWM drivers based on the TCPWM device
to connect with a clock. This update allows multiple devices to connect
to the same peripheral clock, and supports the TCPWM architecture of the
PSC3 device family.
Corrects initialization of the PWM on the PSC3 family to select the
correct output type.
Signed-off-by: John Batch <john.batch@infineon.com>
Add implementation of the Infineon PSoC4 TCPWM-based counter driver.
- Provides basic counter operations
including start, stop, read, and set alarm.
- Supports configuration and initialization through Device Tree.
- Enables alarm callback handling for
precise time-based event generation.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Refactor the Infineon TCPWM counter driver to use the TCPWM block base
address instead of the counter instance base address. This change aligns
with the standard Infineon PDL API which requires the TCPWM block base
and counter index as separate parameters.
This modification maintains functional compatibility while providing
better alignment with the underlying hardware abstraction layer.
This also aligns with PR feedback to move the ifx_tcpwm.h header file
from the include folder (public APIs) to the drivers folder. Instead,
this refactoring prepares to remove that header file entirely.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
- Update the driver to support the PSE84 device
- Update to new peripheral clock allocation scheme
Signed-off-by: Bill Waters <bill.waters@infineon.com>
