This adds support for ARM Corstone System Architecture Specification Ma2
(ARM CRSAS-MA2) System Counter and System Timer.
The HW consists of one 64-byt System Counter, and any number
of System Timers that have match registers to generate interrupts
based on the value of the System Counter.
The timers don't have any counter/timer of their own, meaning that
System Counter can't be started or stopped independently if there is an
enabled System Timer.
Add the crsas-ma2 timer to the test for counters.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Krystian Hebel <khebel@antmicro.com>
Commit bbda65a ("drivers: counter: increase COUNTER_INIT_PRIORITY")
raised COUNTER_INIT_PRIORITY from KERNEL_INIT_PRIORITY_DEVICE (50) to
60 to guarantee counter devices initialize before bus-dependent devices
sharing the same default priority.
Revert to KERNEL_INIT_PRIORITY_DEVICE and remove the BUILD_ASSERT in
the RTC counter driver that enforced RTC_INIT_PRIORITY >
COUNTER_INIT_PRIORITY, as both now default to the same value with
ordering guaranteed by DT sub-priority.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
The TTC provides three independent hardware counters supporting
free-running and interval modes, accessed via MMIO registers.
This driver implements the Zephyr counter API, including start/stop,
read, alarm, and top value configuration. Alarm events are delivered
using match interrupts.
Dynamic IRQ connection is used to support platforms where multiple
TTC counter instances share the same interrupt line. Each IRQ is
registered only once at runtime, and the ISR dispatches pending
events to all TTC instances mapped to that interrupt, ensuring correct
handling for both shared and dedicated interrupt configurations.
Signed-off-by: Satya Sri <satyasri.katru@amd.com>
Add a counter driver for the NXP Time Stamp Timer (TSTMR), a 56-bit
free-running, read-only up-counter. The driver exposes it through the
Zephyr counter API (get_value/get_value_64 and get_freq); start/stop,
alarm, and top-value operations are unsupported as the hardware is
free-running with no compare or interrupt capability.
The frequency is SoC-specific and taken from the clock-frequency
devicetree property. A coherent 56-bit read is obtained by sampling the
low/high registers twice under an IRQ lock and handling low-word
rollover.
Add the binding, Kconfig, and build glue.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Remove the deprecated counter-based Maxim DS3231 driver and its
dedicated API, binding, sample, and test coverage.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a counter driver for the Xilinx Zynq Ultrascale+ MPSoC Real Time
Clock. The hardware provides a 32-bit seconds counter driven by an
external crystal oscillator, one alarm channel, and a calibration
register with integer and fractional tick adjustment.
The driver implements the Zephyr counter API and is intended to be used
with the rtc_counter wrapper to expose the standard RTC API.
The RTC oscillator runs continuously so start() and stop() return
-ENOTSUP. Calibration support is gated by CONFIG_COUNTER_CALIBRATION.
Signed-off-by: Harini T <harini.t@amd.com>
Add optional set_calibration/get_calibration operations to the counter
driver API. Calibration is specified in parts per billion (ppb). The
operations are gated behind CONFIG_COUNTER_CALIBRATION and return
-ENOSYS if not implemented by the driver.
Signed-off-by: Harini T <harini.t@amd.com>
Add a counter driver for the MCUX wake timer. The hardware is a
one-shot down-counter with one load/count register, so the driver
uses the register either for periodic top handling or for relative
single-shot alarms.
Absolute alarms are reported as unsupported because programming an
alarm reloads the hardware counter and changes the value space that
an absolute target would be measured against. Clear stale pending IRQ
state around start, stop, cancel, and alarm setup.
Built and ran tests/drivers/counter/counter_basic_api on frdm_mcxa153
with CONFIG_COUNTER_MCUX_WAKE_TIMER_ALARM=y.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add a Zephyr counter driver for the NXP MCUXpresso System Counter
(SYS_CTR). The driver supports:
- 56-bit free-running up-counter
- Selectable clock source: 24 MHz base clock or 32 kHz slow clock
- Two compare frames (alarm channels) with a shared interrupt
- Standard Zephyr counter alarm API
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
This introduces APIs for input capture.
A use case for this would be time stamping a rising and/or falling edge
where precision and lack of jitter is important. The only way to currently
do this in zephyr is to set up a GPIO interrupt and then read the counter
or kernel time... but this can have limitations of software such as the
processor may have a lot going on and can be subject to interrupt
latencies. Having a hardware 'latch' done of the rising and/or falling
edge with respect to a timer can eliminate these imprecisions.
How this is to be used, is that an application is to call
`capture_callback_set` with the configuration of the channel number, flags
(such as falling, rising, or both edges), and then a callback function.
Then the `capture_enable` function is to be called to enable this. The
callback has the timestamp of the edge in ticks and the edge that it
captured (rising or falling).
This also adds a 64 bit tick version for the capture callback.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add counter RTC driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Basic counter operations
- Alarm configuration and callbacks
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add counter timer driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver is based on the hardware timer and supports:
- Relative alarm configuration
- Top value configuration
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add a kconfig to be used as a flag for indicating if it supports 64b
ticks and another flag which will enable the 64b api. The kconfig
indicating that it supports 64b is a dependency of the kconfig that
will enable the api.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some counters, such as those that use fractional adders, tick at
resolutions greater than 4294967295Hz. This changes the freq in the common
info to a uint64_t. This adds a KConfig that can be selected by a driver.
This also has the counter ticks to sec (and vice versa) helper functions
call the get frequency for 64 bits if the kconfig is selected.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Added a counter driver for the RPI Pico/RP2040 that implements
programmable interval timer (PIT) functionality using the PWM HAL.
Signed-off-by: Jan Behrens <jan.behrens@navimatix.de>
Expose timer functionality from rv-3032-c7 via counter api.
I2C communication and IRQs are arbitrated via MFD parent driver
for rtc, sensor and counter at once.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
This commit enables configuration and integration of LCT counter by
including relevant source and kconfig files.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
- Add a new counter driver implementation based on the PDL for
Infineon CAT1B devices. This enables support for hardware
counters on the PSC3M5 platform.
- Add IFX_TCPWM_Counter_DeInit and IFX_TCPWM_Counter_Init
macros to include/zephyr/drivers/timer/ifx_tcpwm.h
and sort all of the macros in that file
Signed-off-by: Yurii Lozynskyi <yurii.lozynskyi@infineon.com>
1.Update dts bindings to move clock-source properties from
nxp,ftm-pwm.yaml to nxp,ftm.yaml.
2.Provide counter driver based on FTM driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
1.Add dts bindings nxp,lpit-channel.yaml and nxp,lpit.yaml
2.Provide counter driver based on lpit driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Counting module, Capture block (measure input signal period/time) and
Compare block (to generate time expiry, output waveform like PWM).
Add a support for counter driver with alarm and counter top functions.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add support for cc23x0 RTC driver in counter.
RTC is always ON after device boot. Timer is restared only
on POR, and is active during STANDBY and ACTIVE power states.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
The IT8xxx2 timer driver uses timer 7 and timer 8 to implement the alarm
timer and the top timer, respectively.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
Including renaming the DTS binding and kconfig options
deprecating the old one.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Common RTC counter driver for MAX32xxx MCUs.
Time of day alarm is used to generate interrupt.
The resolution of time of day interrupt is 1Hz.
Subsecond alarm interrupt not works it does not meet
zephyr counter driver requirement, so that not used.
To use as wakeup source wakeup-source parameter shall be
defined as below
&rtc_counter {
status = "okay";
wakeup-source;
};
Co-authored-by: Okan Sahin <okan.sahin@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
- boards: renesas: Add support for agt.
- drivers: counter: Add support for counter driver use agt
- dts: arm: Add support for agt.
- dts: bindings: Add support for agt counter driver.
- soc: renesas: Add support for agt counter driver.
- samples: drivers: counter: alarm: Add support for RA8
This is initial support with only basic functionality for counter
operation on Zephyr using AGT hardware, current support for
count source is limited to LOCO and PCLKB, other count source
like underflow signal external pin or AGTIO from another AGT
channel will be added in later support
Signed-off-by: Ha Nguyen <ha.nguyen.fz@bp.renesas.com>
Signed-off-by: Thao Luong <thao.luong.uw@renesas.com>
Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Common counter driver based on timer for MAX32xxx MCUs
To use as wakeup source wakeup-source parameter shall be
defined as below
&lptimer0 {
status = "okay";
clock-source = <ADI_MAX32_PRPH_CLK_SRC_ERTCO>;
wakeup-source;
counter {
status = "okay";
};
};
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
