Commit graph

13 commits

Author SHA1 Message Date
Thomas Stranger 0d7abdf012 drivers/clock_control: stm32 common fix STM32_SRC_PLLCLK calculation
Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.

This commit resolves this issue for l0, l1.

get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-07-27 18:44:49 +02:00
Thomas Stranger ddf3f2d735 drivers/clock_control: stm32 common allow pll also when it is not sysclk
The SOC specific implementations of the clock_stm32_ll_common driver
included the PLL specific functions only when PLL was selected as sysclock.

This commit changes the condition from "STM32_SYSCLK_SRC_PLL"
to "defined(STM32_PLL_ENABLED)".
As a result the pll could also be used as peripheral clock source
in case it is not the sysclock.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
2022-07-04 16:41:24 +02:00
Erwan Gouriou 09217865ce drivers/clock_control: stm32_common: Implement clock source selection
Similarly to what was done on U5 and H7 clock_control drivers, enable
device clock source selection.
This is done by:
-providing implementation for clock_control_configure().
-updating clock_control_get_rate() to support various possible clock
sources (SYSCLK, PLLCLK, LSE, LSI, HSI, HSE).
-providing enable_clock() to verify requested clock source exists and
is enabled.
-adding LSI and LSE device tree based initialization to
set_up_fixed_clock_sources().

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-10 18:42:30 +02:00
Gerard Marull-Paretas fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Erwan Gouriou c4ff7d1e19 drivers/clock_control: stm32_common: Add elementary PLL configuration step
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.

To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-04-21 14:09:44 +02:00
Erwan Gouriou 391cd36e70 drivers/clock_control: stm32 l0/l1: Update for DT based configuration
Add required changes to support DT based configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 16:41:26 +02:00
Erwan Gouriou 99f211b668 drivers/clock_controller: stm32: Prepare for dts based configuration
To allow transition to device tree based clock configuration on
stm32 targets, rework clock_control driver to use intermediate
STM32_ macros initially defined as the equivalent Kconfig macros
for now.
Propagate the change in all code using these macros.

The reason to introduce these new macros instead of configuring
Kconfig flags using dt kconfigfunctions is that we'll need
to be able to inform users that Kconfig flags are deprecated
once the whole family conversion is done, to encourage
out of tree users to adopt this new configuration scheme.

Note: For now STM32H7 series and code is excluded.
This is the same for some series specific code such as
PLL mul/div for L0/L1 and XTRE prescaler on F1 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 16:41:26 +02:00
Martin Jäger d5aff7ba3c drivers: clock_control: stm32: use generic LL headers
Use generic LL headers instead of depending on soc.h.

Signed-off-by: Martin Jäger <martin@libre.solar>
2020-11-30 15:50:03 +01:00
Andreas Sandberg f1d80b3f02 drivers: clock_control: stm32: Enable SYSCFG on STM32L0
The entropy driver needs to use the SYSCFG block to control VREF on
the STM32L0. Clock the block if the entropy driver has been enabled.

Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
2020-06-09 14:44:25 +02:00
Peter Bigot 0b0d2e640b treewide: use full path to clock_control/stm32_clock_control.h header
The build infrastructure should not be adding the drivers subdirectory
to the include path.  Fix the legacy uses that depended on that
addition.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-26 17:52:12 +01:00
Anas Nashif a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif 17ddd1714c cleanup: include/: move clock_control.h to drivers/clock_control.h
move clock_control.h to drivers/clock_control.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Erwan Gouriou 37c13eec7a drivers/clock_control: stm32: Factorize series specific code
RCC device could be common to various STM32 series.
Until now, PLL handling code was set in series specific files,
even if it was driving the same device than another series.
Minimize code duplication by factorizing code between series
when possible.
With this change, some series get additional features by getting
access to code developed for other series.

Additionally, while renaming the files, remove the non informative
'x' to minimize file name length

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-10 10:53:11 -04:00
Renamed from drivers/clock_control/clock_stm32l0x.c (Browse further)