Based on edit done at r8a779f0 driver creation
(f5634a1a0e6f607809a7e4b8d1933a85b5eb7642)
following comments on #56043.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Remove old unused defines from header
Use clang-format to apply coding guideline to r8a7795 driver
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Add MMIO mapping for Renesas CPG driver in order to avoid
mappings inside mmu_regions.c file. Remove MMU region for
Renesas CPG driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associative tables for core and mod clocks.
Add possibility to enable/disable any of core clocks which presents
in the associative table.
Add handler for setting rate to driver and use generic rcar cpg
function for getting rate.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add associated tables of clocks and API for working with these tables,
from this moment the relationship between clocks and their divider are
built. After set rate of some Core clock, driver has to update all
in/out rates of all childrens recursively. During get/set rate calls
if out rate is unknown, we try to get parent in/out rates and its
divider, in case when parent doesn't have valid in/out rates we get
parent of parent and so on until we get parent with a valid in or out
rates.
Add generic Renesas functions for get/set rate of CPG.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Move cpg log module declare to common rcar cpg file. If the module
consists of multiple files, then LOG_MODULE_REGISTER should appear
in exactly one of them. Each other file should use LOG_MODULE_DECLARE
to declare its membership in the module.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add R-Car Gen3 PWM driver.
Clock diviser is automatically adjusted according to requested period
and duty-cycle in order to obtain as much accuracy as possible.
Indeed, in order to improve PWM accurancy, the PWM clock has to fit
the requested period. So use the given period_cycle to define if the
clock as to be adapted. In such case, increase/decrease the clock
diviser to adapt the period_cycle and be sure that it fits into the
10 bits counter of the PWM controller.
Tested on H3ULCB on pwm0 and pwm4.
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
ASSERT was failing when `r8a7795_cpg_mssr_start_stop` was
called for a "core" clock.
This ASSERT statement and "mstpcr" table of registers are
only meant to be used when starting or stopping a "module" clock.
Moved ASSERT statement to `rcar_cpg_mstp_clock_endisable`
as well as "reg" & "bit" calculation.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit rewrite renesas R-Car clock driver in order
to be able to support any new SoC easier.
This work is so creating a clock driver per soc alongside a
common driver for all reneasas r-car boars.
- drivers: create a driver per soc
- create a common driver
- create a common header used by soc & common driver
- create a soc specific driver calling for common driver
- dts: use new compatible
- use old yaml as common yaml
- create a new "child" yaml to define the new compatible field
- change compatible in device tree
As in Linux, the driver can support both r8a77951 and r8a77950
SoC's so we decided to name the new driver as in Linux with Zephyr
prefix : "clock_control_r8a7795_cpg_mssr.c".
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
