Commit graph

16 commits

Author SHA1 Message Date
Pieter De Gendt
c25e31512c drivers: clock_control: Place API into iterable section
Add wrapper DEVICE_API macro to all clock_control_driver_api instances.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2024-11-29 21:46:34 +01:00
Pisit Sawangvonganan
847a4eaad2 style: drivers: comply with MISRA C:2012 Rule 15.6
Add missing braces to comply with MISRA C:2012 Rule 15.6 and
also following Zephyr's style guideline.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-09-11 07:40:35 -04:00
Fin Maaß
de82190e13 drivers: clock_control: litex: remove redundant entry
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-07-12 05:49:01 -04:00
Pisit Sawangvonganan
dc5527721a drivers: clock_control: remove '&' when assigning clock_control_xxx_init
Remove address-of operator ('&') when assigning `clock_control_xxx_init`
function pointer in `DEVICE_DT_INST_DEFINE` macro.

This change aims to maintain consistency among the drivers in
`drivers/clock_control`, ensuring that all function pointer assignments
follow the same pattern.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
2024-06-27 08:50:20 -04:00
Benjamin Cabé
22535a99ab drivers: clock_control: litex: declare unmuttable map as const
Save precious RAM by declaring DRP reg->size map as const as it's
immutable

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2024-06-13 08:02:26 -04:00
François Baldassari
e94af5b153 Litex: clock: Undefined behavior due to unchecked return code
Found via static analysis. Two separate error paths where failing to
check the return code leads to undefined behavior:
1. In `litex_clk_get_phase`, the divider stays set to 0 when
   `litex_clk_get_clkout_divider` errors out, which leads to a division
by 0.
2. In `litex_clk_calc_duty_normal`, the `duty` struct is used
   uninitialized if `litex_clk_get_duty_cycle` errors out.

In both case, checking the return code and returning early resolves the
issue.

Signed-off-by: François Baldassari <francois@memfault.com>
2024-06-10 15:00:33 +03:00
Gerard Marull-Paretas
8edd33bf27 drivers: clock_control: litex: add missing include
Drivers uses custom IO read/write API defined in soc.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-19 15:13:53 +00:00
Daniel Leung
51ff4ced59 clock_control: renames shadow variables
Renames	shadow variables found by -Wshadow.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-08-10 08:14:12 +00:00
Nick Ward
8b9204035a drivers: clock control litex: fix spelling of below
Fix spelling of below

Signed-off-by: Nick Ward <nix.ward@gmail.com>
2023-05-29 05:21:10 -04:00
Gerard Marull-Paretas
fb60aab245 drivers: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all drivers to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:58:21 +02:00
Michal Sieron
2e9154a418 soc: litex-vexriscv: Rewrite litex_read/write
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.

This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.

There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.

Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.

Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.

Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.

Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.

This makes it possible to have code, independent of CSR data width.

Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
2022-04-29 16:11:53 +02:00
Maureen Helm
ed9cb841c3 drivers: clock_control: Refactor drivers to use shared init priority
Refactors all of the clock control drivers to use a shared driver class
initialization priority configuration,
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control
drivers separately from other devices. This is similar to other driver
classes like I2C and SPI.

Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new
option is the lower of the two, which means earlier initialization.

The even lower defaults for STM32 and Arm Beetle are preserved by
SoC-family level overrides.

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-19 23:05:25 -04:00
Gerard Marull-Paretas
62afdca908 drivers: clock_control: remove usage of device_pm_control_nop
device_pm_control_nop is now deprecated in favour of NULL.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-28 10:54:58 -04:00
Anas Nashif
5fa12073cb drivers: remove what appears to be code from comments
Some tools consider this as commented code because of the ifdef, so
remove that and fix a coding guideline violation.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-04-01 05:34:17 -04:00
Kumar Gala
57a402cd0a drivers: clock_control: Convert drivers to new DT device macros
Convert clock_control drivers from:

    DEVICE_AND_API_INIT -> DEVICE_DT{_INST}_DEFINE

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-12-16 15:23:39 -06:00
Pawel Czarnecki
ed6c0103a9 drivers: clock control: Add LiteX clock control driver
This commit adds LiteX SoC Builder clock control driver for MMCM
module. It gives ability to change frequency, phase and duty cycle
on up to 7 clock outputs.

Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-12-06 12:35:16 -05:00