Commit graph

9 commits

Author SHA1 Message Date
Henrik Lindblom
6a3309a9e4 cache: stm32: add cortex-m33 peripheral driver
STM32 Cortex-M33, such as the L5/H5/U5 series, have a cache peripheral for
instruction and data caches, which are not present in the C-M33
architecture spec.

The driver defaults to direct mapped cache as it uses less power than the
alternative set associative mapping [1]. This has also been the default in
stm32 soc initialization code for chips that have the ICACHE peripheral,
which makes it the safest choice for backward compatibility. The exception
to the rule is STM32L5, which has the n-way cache mode selected in SOC
code.

[1]: https://en.wikipedia.org/wiki/Cache_placement_policies

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
2025-04-25 11:04:37 +02:00
Mahesh Mahadevan
c14f55b530 drivers: cache: Cache driver for NXP XCACHE controller
Some NXP SoC's have External cache that is managed by
the XCACHE cache controller.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2025-01-15 22:57:41 +01:00
Wei-Tai Lee
80f9736115 drivers: cache: add Andes cache driver
Add cache driver for Andes cache.

Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2024-04-22 09:19:27 -04:00
Witold Lukasik
6d3009ff2b drivers: cache: add Nordic cache driver
Add Nordic driver for cache.

Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
2024-01-30 21:00:44 +00:00
Daniel Leung
26ecaba4af drivers: syscalls: use zephyr_syscall_header
This adds a few line use zephyr_syscall_header() to include
headers containing syscall function prototypes.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-06-17 07:57:45 -04:00
Henri Xavier
dfededeadf cache: Fix build warning 'No SOURCES given to Zephyr library'
Following 4806e1087e ,
the following warning appears for some boards (e.g. `qemu_cortex_a53`)
```
CMake Warning at /zephyr/CMakeLists.txt:798 (message):
  No SOURCES given to Zephyr library: drivers__cache

  Excluding target from build.
```

Allow this driver to have no sources.

Signed-off-by: Henri Xavier <datacomos@huawei.com>
2022-08-24 10:36:40 +00:00
Carlo Caione
4806e1087e cache: Fix cache API calling from userspace
When a cache API function is called from userspace, this results on
ARM64 in an OOPS (bad syscall error). This is due to at least two
different factors:

- the location of the cache handlers is preventing the linker to
  actually find the handlers
- specifically for ARM64 and ARC some cache handling functions are not
  implemented (when userspace is not used the compiler simply optimizes
  out these calls)

Fix the problem by:

- moving the userspace cache handlers to a their logical and proper
  location (in the drivers directory)
- adding the missing handlers for ARM64 and ARC

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-08-23 10:14:17 +02:00
Dylan Hung
c880db1725 cache: Add Aspeed AST10x0 external cache driver
The CPU in Aspeed AST10x0 SOC is a ARM Cortex-M4 which doesn't internal
cache memory.  Aspeed implements an integrated system level cache to
accelerate instruction and data memory accesses.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-06-05 14:28:50 +02:00
Carlo Caione
e2333269ae cache: Introduce external cache controller system support
The cache API currently shipped in Zephyr is assuming that the cache
controller is always on-core thus managed at the arch level. This is not
always the case because many SoCs rely on external cache controllers as
a peripheral external to the core (for example PL310 cache controller
and the L2Cxxx family). In some cases you also want a single driver to
control a whole set of cache controllers.

Rework the cache code introducing support for external cache
controllers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-05-08 07:00:33 +02:00