The commit f10fa0dea8 mapped the
Cortex-R52 processor type to use the "VFPv3" FPU type, but the
toolchain requires the "FPv5" FPU type and refuses to assemble
floating-point instructions when the "VFPv3" FPU type is specified.
This commit updates the build script to specify the FPU type of
`fpv5-sp-d16` when the processor is configured with a single-precision
FPU, and `neon-fp-armv8` when the processor is configured with a
double-precision + Advanced SIMD-capable FPU.
Note that the `fp-armv8` FPU type is an alias for double-precision FPv5
with 32 double-precision registers (refer to the GCC
`gcc/config/arm/arm-cpus.in` for more details); NEON is always
specified in case of a double-precision configuration because the
Cortex-R52 can only be configured as such.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
The Cortex-R52 processor supports single-precision
floating-point instructions and can optionally support
the double-precision floating-point instructions.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit updates the Zephyr build system to support specifying
advanced floating-point compilation options derived from the newly
introduced unified floating-point configurations.
The following changes are introduced by this commit:
1. Specify architecture floating-point option to the `-mcpu` flag.
2. Specify floating-point unit (FPU) type using the `-mfpu` flag.
Note that the `-march` flag is not specified separately because the
`-mcpu` flag provides more detailed architecture options and this
makes the `-march` flag redundant.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
