Commit graph

7 commits

Author SHA1 Message Date
Yong Cong Sin bbe5e1e6eb build: namespace the generated headers with zephyr/
Namespaced the generated headers with `zephyr` to prevent
potential conflict with other headers.

Introduce a temporary Kconfig `LEGACY_GENERATED_INCLUDE_PATH`
that is enabled by default. This allows the developers to
continue the use of the old include paths for the time being
until it is deprecated and eventually removed. The Kconfig will
generate a build-time warning message, similar to the
`CONFIG_TIMER_RANDOM_GENERATOR`.

Updated the includes path of in-tree sources accordingly.

Most of the changes here are scripted, check the PR for more
info.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-05-28 22:03:55 +02:00
Andy Ross 03cafbdaef arch/xtensa: "NMILEVEL" is an optional feature
Some oddballs cores can be generated without an "NMI" interrupt, in
which case core-isa.h will not define XCHAL_NMILEVEL.  This code is
trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the
pedantically correct choice anyway (NMI's by definition, cannot be
masked).

Signed-off-by: Andy Ross <andyross@google.com>
2024-05-20 20:50:55 -04:00
Andy Ross 6ab7735774 arch/xtensa: Automatically generate interrupt handlers (finally)
The script to generate the _soc_inthandlers.h header has been run
manually for years, only because I was a cmake novice at the time and
unsure how to integrate it into the build.  So every new platform has
to find the script and template file and figure out how to generate
the file.  And in a few cases it looks like we've tried to EDIT the
resulting files in the tree.

Let's finally do this right.  The file is now dropped (for every
xtensa platform) as a "xtensa_handlers.h" file, and there is a Kconfig
to control whether the original/manual file or the new one is used by
the platform code.  We can migrate the other platforms slowly as
people have time to validate.

Signed-off-by: Andy Ross <andyross@google.com>
2024-05-20 20:50:55 -04:00
Daniel Leung 57d591700b xtensa: mpu: enable userspace support
This extends the Xtensa MPU to support userspace.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-03-19 22:17:34 -04:00
Maciej Kusio 352b50bfc9 xtensa: add support for cores without NMI
Some Xtensa cores do not support NMI, so XCHAL_HAVE_NMI=0 and
XCHAL_NMILEVEL won't be defined at all causing
arch/xtensa/include/xtensa-asm2-s.h to throw compilation error.

Fixes: #67855

Signed-off-by: Maciej Kusio <maciejkusio@meta.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2024-02-28 17:35:54 +00:00
Daniel Leung 545cf8cd2f xtensa: print THREADPTR when dumping stack
Print THREADPTR when dumping stack just like other registers.
There is no need to guard that behind CONFIG_USERSPACE.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-02-01 13:09:53 -06:00
Daniel Leung 0636e52eff xtensa: rename xtensa_asm2.c to vector_handlers.c
Rename xtensa_asm2.c to have a more meaningful name to actually
reflect the content of the file. This file is mostly about
handling interrupts and exceptions (via the predefined vectors
in Xtensa core).

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Renamed from arch/xtensa/core/xtensa_asm2.c (Browse further)