Adds two new fields to the ISR_LIST structure (irq and priority) to allow
the decoupling of the vector ID and priority from the IRQ number at some
future time.
As a result of the addition of these two new fields, the gen_idt tool is
modified to both process these new fields as well as validate them.
Change-Id: I343dac68d99c78168a25b19784140f85d5db7578
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Instead of using logic choosing between invoking find_lsb_set() and
find_msb_set(), mask out the unwanted bits and always invoke find_lsb_set().
This also has the side benefit of simplifying the error checking when DEBUG is
enabled.
Change-Id: I7f3e529ab3807b4433291197793e79e371d06ae3
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
When dyanmicaly connecting an interrupt via irq_connect(), interrupts must be
locked both when allocating a dynamic interrupt stub and when updating the
interrupt descriptor table (IDT) to prevent race conditions.
Change-Id: I9c68c1f73dda478880f1a32793a84cb6eb87735e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Move Zephyr specific CFLAGS that depend on config options to
the Makefile where they can better be managed among other cflag
options.
Change-Id: Ia79a2f2def4f51857f6d661aa78e9fb7eb7a5e22
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use micro_* or nano_* defconfigs, instead maintain platform
in one single defconfig and merge nano or micro support on top.
Change-Id: I0d5184f37865ed8312e516e48cf5a8584a287dfe
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Setting up the right SPI port, its configuration and max frequency.
Also, setting NANO_TIMEOUTS by default as it is required for delayed
operation inside ADC's driver.
Change-Id: I63b2b872ff858f1d80065a94ba3e2f303d279a67
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Taking the opportunity to set simpler driver names for port 0 and 1.
Change-Id: I994bc43daaf6bc43b0dad564a72577c874f72d2d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
*_PORT_1_* not *_PORT_0_* obviously.
Change-Id: Idefad40c25b4ad54d9558355daab224bc634c2e7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Galileo SPI interrupt is of type level low, thus setting it to this
value in Galileo's defconfig and removing useless entry in Kconfig.
Change-Id: I90bcc74be1a957bf59912d6f8c2234cfa4fe2329
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Needed to get simple uart driver working in qemu with
SLIP networking or qemu<->qemu network testing. Because
this is only needed in qemu the patch only touches ia32
platform.
This can conflict with Bluetooth in x86 and qemu so caveat emptor.
Change-Id: Iba20543f968c8fd37ee36747d9aa1ad3f782057d
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Kconfig can't set the default for a choice, so it has to be done
using select.
Change-Id: I1d952eb48a7bcda79b4f8ff475110c7430be7b4e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
do not use microkernel or nanokernel as the output binaries,
instead, use zephyr globally.
Also change the documentation to reflect this.
Change-Id: I8405761d1a0392c90cdfeec5c67d72eb4e5a76ff
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
PCI information and integration of designware's gpio controller
with shared irq.
Change-Id: I80c7fed35ff328e06d87ebad3e2f68fdd6f5672e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Since the console is not yet setup, there will be nothing to be printed
out. Also, it adds a dedicated init function which is only useful for
it. Instead, debugging PCI enumeration can be simply done in application
side.
Change-Id: Ia8384caa97d43f0bc4300ecf36bc11d1b8bd5581
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
As long as PCI_ENUMERATION does not work for all IP block, let's provide
pre-configured base address registers for ns16550 on Galileo.
Once PCI_ENUMERATION will be fixed, such pre-configured settings will
not be used at runtime.
Change-Id: I514b3a5759e3af04132c7801f37033108a7b279b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Providing the right settings through Galileo's Kconfig.
Change-Id: Ia5339eb90cb98d7dde3be0493bcfd9a6b6db60ed
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add Kconfig option to specify how interrupt is triggered for SPI.
Also enabling such support for Galileo platform.
Change-Id: Id3112d100089197940f826b827493174d0f22669
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Perform configuration of the shared IRQ has to be done earlier,
as the config code masks the interrupt by default. If configuration
is done after shared_irq_enable() is called, the interrupt is
effectively masked. So move the init level a bit earlier.
Change-Id: Ic7f059628e3cf122d323513e171c7d1a09e5d4a6
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IOAPIC driver resets all interrupt vectors, so any configuration
has to be done after that. Move the HPET IRQ config to later init
level so we are sure that the configuration is being done.
Change-Id: Id169461cce15252f7fb77e9c07961300233f3344
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
With the typos, IRQ triggering conditions are not set correctly.
Change-Id: I0698ce69c3368411a2f91a32ac27608e9f1de252
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This expands the Galileo pinmux driver to configure the GPIOs
on the DesignWare IP block, and the core/resume wells on
the legacy bridge.
Change-Id: Ia1df4b6fd3b104f08563fe9eab93f01efbb53b66
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This enables all the GPIO blocks, and pin muxes on Galileo Gen2
board. GPIO and I2C are now sharing one interrupt line so both
can now get interrupt driven events.
Change-Id: I31a4823abba84539ce5d1cc84e85b7dc335cf831
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Debugging should only enabled in the application using this
platform, not for everyone.
Change-Id: If5c17d0a87ac1d15d19ece7de93102eb2461c324
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The Kconfig option SUPPORT_FP_SHARING does not exist. In fact, it had been
previously renamed to FP_SHARING (this one case was missed). Fixing this
allows the use of conditional directives in _ExcExit() to be simplified.
Change-Id: I61f98191afe776f70af3c9d9265c38c559be3486
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Fixes the initialization of the default exception stack frame to ensure that
every field of the structure is initialized to the dummy value of 0xdeaddead.
Change-Id: Ic7a5b66204172b53a657c9540196f01a74e1000c
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The DesignWare GPIO and I2C are PCI devices which share the same
IRQ line. This patch enables the shared IRQ support for I2C. GPIO
support is to be followed.
This also enables I2C for nanokernel on Galileo.
Change-Id: I66681d71899914bdcb35c4af649d077ffb8d7970
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On some platforms (e.g. Galileo), the I2C controller is on PCI bus,
which shares IRQ with other devices (GPIO on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: Id4e4714aed37c2893d0ffe9ed1e4edaabb338121
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
On some platforms (e.g. Galileo), the GPIO controller is on PCI bus,
which shares IRQ with other devices (I2C on Galileo). This patch
adds support for utilizing shared IRQ.
Change-Id: I4b44bae15356e4710d54f0343fed1bd27f35e484
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the code to setup the IO-APIC for shared IRQ.
The code to enable shared IRQ with GPIO and I2C will follow.
Change-Id: I6e7de69f83bf7f1dd0da0571dbcb417beb2c232b
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This driver allows multiple drivers to share a common interrupt
line. This functionality is required on system that conform to the PC
interrupt structure. In the context of Zephyr this is needed for
SOC's that have their I/O IP blocks behind a PCI interface. Due to the
limited number of interrupt lines provided by the PCI interface
multiple IP blocks may be configured to share an interrupt line.
Drivers that share interrupts must be modified to *not* register their
own interrupt service routine as part of their configuration/initialization
but instead bind to the correct instance of this driver by name, then
register their interrupt service routine with this driver.
Change-Id: I57b517b97ebeabce484ba53c8f940da993cb391d
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The first 32 entries are for well-known exceptions
Change-Id: I3342c48af6e7f687065fafd0c2af4dabc04d421e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The GPIO ports on the legacy bridge have to be access by
I/O port read/write, instead of direct memory access.
Choices in Kconfig cannot have default values in Kconfig,
so it has to be done in defconfig instead.
Change-Id: I479f3776edf5690f73d8e857ce6683285db092c0
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The interrupt selectionss are no longer specific to a particular
controller (e.g. I2C_DW_0), but apply to all controllers on
the platform.
[DL: Extracted these changes into their own patch, instead of
being squashed with others. Also modified the Kconfig
options to move them into proper position.]
Change-Id: Idc7ac9769e947447b868dccf772a95dbb5fc8021
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This adds the default config option to enable the I2C controller,
for both nanokernel and microkernel.
Note that choices in Kconfig cannot have default values in Kconfig,
so it has to be done in defconfig instead.
Change-Id: I2ac0c880629db68e5b9a6bf61e49939ab7418a89
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the Kconfig option to specify default configuration
for the I2C controller during driver initialization.
During boot, the controller needs to be configured before
communication to slave devices can start. After boot,
an app can re-configure the controller if needed.
Change-Id: I7bf252f75a31943ae444e4d914f3a9a1a3f3d91f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Begining of interrupt (BOI) is only supported on systems with a 8259
interrupt controller all modern x86 systems use APIC interrupt
controller.
Change-Id: Ife2b3b1971bbebeda597bfa1f96005f79cd7e959
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Zephyr requires that the processor be in 32 bit protected mode on
entry.
Change-Id: I71792eeb154281881e8516a7a8a2291a52f83fc6
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
BOOT_A20_ENABLE relies on the kernel being on a system that has a full
PC BIOS and requires that the A20 line be enabled to boot
correctly. None of the supported platforms satisfy either requirment.
Change-Id: I05805a050f5531de0348b60a4f0cb974e464b279
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
This avoids the case where the system has multiple threads using
floating point and the threads were not properly configured to use
floating point. The misconfigured threads will only take the fault on
first use of a floating point instruction.
Change-Id: I2be9f9f145bc4e7659e07154021ccc237774897b
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Allow the user to see the configure option without relying on
FP_SHARING being set.
Change-Id: I7e802c18a1c1087f7672925b18ae32dcc20787da
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The default for x86 floating point support in Zephyr is *no* this
option is redundant and more that a little confusing.
Change-Id: I41fad33467321c483a4df028230ecbb28b4486f9
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
SSE instructions are controlled by the FLOAT and SSE config variables
this option is redundant
Change-Id: Iab43d21315655a00daeac24994ee29a8e1c70207
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The projects depend on the options enabled by ENHANCED_SECURITY select
required options explicitly. Forcing selection based on
ENHANCED_SECURITY is redundant.
Change-Id: I4473996355e67c99be91413b55d7c6685d9263b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
There are devices that need are part of the architecture core the need
to be initialized prior to devices that are integrated around a core
to make up a complete SOC. Namely the interrupt controller in the SOC
must be configured in order to allow the integrated IP blocks drivers
to initialize correctly.
Change-Id: I0a91e08f98516a7b7dd402ffc6494a071f1326b2
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
