Commit graph

4 commits

Author SHA1 Message Date
Martin Åberg fd4e66499c SPARC: Update the Flush windows software trap
This commit re-implements the SPARC V8 ABI "Flush windows" software
trap. The trap is generated by C++ compilers for exceptions and also by
the C standard library function longjmp().

There were two issues with the previous implementation:
1. It did reads and writes via the stack pointer of the trap window,
   which is not defined.
2. It executed with traps enabled but without the processor run-time
   state set to safely handle traps. In particular there was no valid
   stack for trap processing. Even though interrupt priority was set to
   highest level, the behavior at other traps was not deterministic. For
   example non-maskable interrupt (15) trap or bus error trap for
   instruction fetch.

This new implementation does not store backup copies of CPU registers to
the stack, and it executes with traps disabled.

Fixes #63901

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2023-10-25 09:54:31 -05:00
Gerard Marull-Paretas 4b91c2d79f asm: update files with <zephyr/...> include prefix
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Martin Åberg aa0a90d09c SPARC: add the Flush windows software trap
This commit implements the SPARC V8 ABI "Flush windows" software trap.
It enables support for C++ exceptions and longjmp().

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-05-28 06:32:36 -05:00
Martin Åberg 07160fa153 arch: Add SPARC processor architecture
SPARC is an open and royalty free processor architecture.

This commit provides SPARC architecture support to Zephyr. It is
compatible with the SPARC V8 specification and the SPARC ABI and is
independent of processor implementation.

Functionality specific to SPRAC processor implementations should
go in soc/sparc. One example is the LEON3 SOC which is part of this
patch set.

The architecture port is fully SPARC ABI compatible, including trap
handlers and interrupt context.

Number of implemented register windows can be configured.

Some SPARC V8 processors borrow the CASA (compare-and-swap) atomic
instructions from SPARC V9. An option has been defined in the
architecture port to forward the corresponding code-generation option
to the compiler.

Stack size related config options have been defined in sparc/Kconfig
to match the SPARC ABI.

Co-authored-by: Nikolaus Huber <nikolaus.huber.melk@gmail.com>
Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-13 14:53:55 -08:00