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3 commits

Author SHA1 Message Date
Carlo Caione 6503795dc1 riscv: Introduce BitManip extensions 
Add Zba, Zbb, Zbc and Zbs BitManip extensions.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2022-08-29 16:57:18 +02:00
Carlo Caione 5fece03d7d riscv: Introduce Zicsr and Zifencei extensions 
And enable the new extensions on all the SoCs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2022-08-29 16:57:18 +02:00
Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig 
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
 2022-06-05 14:28:42 +02:00