As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.
Also rename various node labels to match the SoC docs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a YAML, DTS node and driver support to utilize data from devicetree
for register address and driver name.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Generic FSK controller enables radio operation
using a custom GFSK/GMSK or MSK modulation format
achieved by programming a set of PHY variables such
as BT product, modulation index and modulation filter
co-efficients (such that max frequency deviation
<= 500kHz). Generic FSK mode also offers a highly
configurable packet structure, variable bit rate
transmission and reception, some limited packet
(header) processing, and interface to a RAM-based
Packet Buffer.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Add SPI driver and bindings for LPSPI peripheral for the RV32M1 SOC.
Based heavily on the existing mcux LPSPI driver.
Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
Remove the handcoded multi-level IRQ values in device tree. We now are
able to generate the encoded multi-level IRQ value.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Each intmux block acts like 8 interrupt controllers in which we can
have multiple device interrupts on a single channel and that channel
than interrupt than chained to another interrupt controller (in the
case of the RISC-V cores, it is the event unit).
So to describe things better to properly be able to walk the interrupt
chain in the device tree we treat each channel in the interrupt mux as
an interrupt controller rather than the intmux as a single interrupt
controller.
In the future this will allow the device tree generation code to walk
the interrupt chain from the device and up through any interrupt
controllers to generate the IRQ value that Zephyr expects (rather than
us hard coding this into the DTS).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-08-02 13:54:48 -07:00
Renamed from dts/riscv32/rv32m1_zero_riscy.dtsi (Browse further)
