Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
Update the hal_nordic module revision, to switch to nrfx 2.1.0.
Because the list of peripherals for nRF5340 has changed as follows:
- SPIM2 has been renamed to SPIM4
- SPIM2-3, SPIS2-3, TWIM2-3, TWIS2-3, and UARTE2-3 have been added
a couple of related corrections needed to be applied in dts and Kconfig
files, plus the spi_nrfx_spim driver has been extended with the support
for SPIM4.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This checks if the DMA controller supports or not
the memory-to-memory transfers. For DMA Version1,
in the stm32f2xx, stm32f4xx, stm32f7xx series,
only DMA instance 2 is able to transfer mem-to-mem.
For other series, with DMA Version2, there is no such a limitation.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit adds initial support for the Silicon Labs EFM32
Giant Gecko GG11 StarterKit.
Features supported for now are NVIC, SysTick, GPIO, Flash,
Counter, I2C, UART and Ethernet. Support for Watchdog and
ADC will follow as soon as their respective PRs are merged.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
Currently, only the stm32h747 soc is supported in the h7 foler.
The h7 series comes with both single core and dual core products.
This change moves C-M4 core out of stm32h7.dtsi so that it can be
included by single core STM32H7 soc description.
Signed-off-by: Moonkwun Jung <mkainyh@gmail.com>
Fix the RTC device tree node for the NXP K6x SoC series. This device
is compatible with nxp,kinetis-rtc.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
STM32L073 soc variant is a STM32L072 with LCD peripheral.
Reflect this in dts definition by including stm32l072.dtsi
in stm32l073.dtsi.
This also allows to fix an issue on stm32l073 gpioe which
declared wrong reg definition.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The I2C controllers on the MEC1501 SoC can be attached to
different I2C output line. For example, the I2C #0 controller
can be used with I2C7 physical lines out of SoC. The output
selection is done by the attribute "port_sel". This renames
the parent I2C nodes on the SoC side to refer to
the controller themselves instead of the output lines to
avoid confusion. The labels of these nodes are also renamed
to reflect the controllers.
On the board level, the DTS labels are overwritten to indicate
the actual output lines.
Aliases are also provided in both SoC and board levels to
provide shortcuts to the DTS nodes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag
aren't currently supported and we are removing them as such. If anyone
is interesting in supporting this platform we can easily recovery it
from git.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis K6x SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add device tree nodes for the internal temperature sensor in the NXP
Kinetis KE1xF SoC series.
A temperature sensor node is added for each ADC in the SoC to allow
the user to choose which ADC instance to use for the sensor readings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added dts additions for stm32 nucleo f767zi board, also added
and modified soc addtions for thet board.
Updated dts reference file name.
Updated yaml to take out adc for now.
Signed-off-by: Roland Ma <rolandma@yahoo.com>
The amount of lock regions differs between different sam0 MCUs.
saml10: 2
saml11: 4
samd2x: 16
saml2x: 16
samd5x: 32
ASF does not provide a definition for this, so create a new one
in dts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Refactors the mcux gpt driver to use generated device tree macros
directly. Removes now unused dts fixup macros from i.mx rt socs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all lpc socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx 6/7 socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all i.mx rt socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Defines device tree aliases for on-chip peripherals at the soc level
instead of the board level for all kinetis socs. The eliminates some
duplicate code in the board level device trees, and will allow drivers
to use device-tree generated macros directly instead of through dts
fixups.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add device_type DTS property in sram0 and sram1 nodes,
for nRF5340 Application and Network CPU, respectively.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit fixes the following problems with the RPU device tree:
1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
Cortex-R4.
2. RPU and APU use different interrupt controllers (PL390 GICv1 and
GIC-400 GICv2, respectively) mapped to the same CPU local bus address
region but with different offsets for the distributor and CPU
interrupt control register sets. The GIC address mapping specified by
the current dts is that of an APU and does not apply to the PL390
GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
Reference" document from Xilinx for more information).
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Rename the NXP FTM instances in the KE1xF SoC to PWM to match the
other SoCs/boards using the FlexTimer as PWM generator.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This patchset enables USART3 on the 96Boards STM32 Mezzanine.
It is broken out to J10 Grove Connector.
Changes:
- Enabled USART3 in board dts.
- Updated board index.rst with uart pinouts.
- soc dtsi: enabled usart3.
Test: Tested USART3 as console at 115200 baud
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine.
SPI4 has been broken out to a Grove Connector on the board.
Changes:
- Updated board dts to enable spi4
- Updated board Kconfig
- Updated board documentation
- Update board pinmux
- Updated stm32f4 pinmux header file
- Updated stm32f401 dtsi
- Updated stm32f4 defconfig to enable PORTE GPIO
- Added board to spi_loopback test
Test: spi_loopback test passed
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
Adds spi device tree bindings and nodes for the lpc54xxx and lpc55s6x
socs in preparation for adding a new spi driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The GIC-400 driver currently only supports SPIs because the (32) offset
for the INTIDs is hard-coded in the driver. At the driver level there is
no really difference between PPIs and SPIs so we can easily extend the
driver to support PPIs as well.
This is useful if we want to add support for the ARM Generic Timers that
use INTIDs in the PPI range.
SPI interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15].
This commit adds interrupt 'type' cell to the GIC device tree binding
and changes the 'irq' cell to use interrupt type-specific index, rather
than a linear IRQ number.
The 'type'+'irq (index)' combo is automatically fixed up into a linear
IRQ number by the scripts/dts/gen_defines.py script.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add device tree elements for all gpio ports of the efr32mg12p including
the dts fixup entries.
Also remove gpio port e since this is not available in efr32mg12p socs.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
NXP's LPC family of MCU's GPIOs parameters is udated.
Boards LPC54xxx and LPC55xxx have updated values according
pin and interrupt layout.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit adds basic support for nRF52833 SoC.
Changes affect introducing:
- architecuture files (dtsi)
- configuration of nrfx drivers
- adaptation of inclusions based on chosen SoC
- configuration of NFCT_PINS_AS_GPIOS depends on HAS_HW_NRF_NFCT.
Signed-off-by: Emil Obalski <emil.obalski@nordicsemi.no>
This patch introduces the support of the Low Power Timer
for the STM32WBxx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SPI NOR driver requires that the size (in bits) be provided in the
devicetree node. Update the binding to make the property required,
and update all nodes based on the memory chip identified.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This patch introduces the support of the Low Power Timer
for the STM32L4xx from STMicroelectronics.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds supoprt for the Atmel SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the sam0 Cortex-M0+ and saml1x Cortex-M23 parts.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Introduce a standard watchdog alias 'watchdog0' that can be utilized
by sample/test code in the future. This helps remove the need for
CONFIG_WDT_0_NAME in dts_fixup.h files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
dts pinctrl definitions were pushed in tree without the code
available to deal with it. They have been kept waiting for the
code, but this is taking much more time than initially thought.
So in current zephyr tree, for all STM32 boards, we have pinmux.c
file which is used to configure pins and these files that are
basically no-op. This situation is creating a lot of confusion
especially to new comers, and create useless maintenance effort.
Remove these files for now.
When zephyr will ready to use them, this commit could be reverted.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit moves DMA parameters previously hard coded in the driver
to the dts.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There is no APB2 bus on stm32f0 series.
What could be found as APB2 in CMSIS files is actually
second group of APB (A.K.A APB1_2).
Fix nodes that are using this wrong reference accorss the series.
Fixes#20310
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move the selection of the IP clock source for the modules in the NXP
Kinetis KE1xF SoCs from being hardcoded in soc.c to being specified in
the device tree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
STM32L151XB-A SoC is almost similar to the STM32L151XB SoC except that
it has more RAM (32KiB). Hence add devicetree and Kconfig support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Indtroduction of generic device tree bindings for keyboard scan devices.
In addition, device tree node entries and dt specific bindings where
also implemented for Microchip MEC1501
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
STM32L1 uses the same spi controller as STM32F1 so we can just set the
right addresses and enable them. We also need to add the fixup names and
to correctly include the header for ST LL HAL.
Signed-off-by: Karl Palsson <karlp@etactica.com>
1. Replace the non-existent CPU device binding ("Cortex-R") specified
by the CPU node with a proper one.
2. Relocate CPU node declaration to SoC dtsi:
The CPU node should be declared in the SoC dtsi because the core
type is SoC-dependent. In fact, this is exactly how it is done in
the Cortex-M port.
3. Remove core_intc (supposedly Cortex-R VIC):
Unlike the NVIC of Cortex-M, the VIC of Cortex-R is not a true
interrupt controller in the conventional sense and merely acts as
a CPU input port for aggregated interrupt request and vector index
signals. For this reason, there is no point in declaring it in the
device tree and specifying it as an interrupt parent. All SoCs
incorporating Cortex-R implement a separate true interrupt
controller (for instance, GIC for Zynq MPSoC and VIM for Hercules).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The patch adds initial support for STM32F030X4 SoC.
STM32F0 Cube package advises to use 'stm32f030x6' code
for both STM32F030x4 and STM32F030x6 SoC variants.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Add soc and dts files to support for most of the common peripherals
in the STM32G4 series. Add specific support for the STM32G431RB.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
Add #pwm-cells property in bindings for Nordic PWMs and add this
property with a suitable value assigned to all PWM nodes in dts
files for Nordic SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for DTS nodes
representing different types of Nordic SPI peripherals. Previously
"nordic,nrf-spi" was used for both SPI and SPIM. SPIS was already
handled separately.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/spi/
new binding for "nordic,nrf-spim" is added and common fields for all
3 types of Nordic SPI peripherals are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in spiX nodes are updated (when there is no
choice as only one type of SPI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/spi/
spi_nrfx_spim driver is updated with the new form of macros generated
from dts
* boards/
all spiX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of SPI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (SPI_x_NRF_SPI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit introduces separate "compatible" strings for dts nodes
representing different types of Nordic TWI peripherals. Previously
"nordic,nrf-i2c" was used for both TWI and TWIM, and TWIS was not
supported.
Quite a few files need to be touched by this commit but the changes can
be divided into groups of related or very similar ones, distinguishable
by the initial part of the path to the modified file:
* dts/bindings/i2c/
new bindings for "nordic,nrf-twim" and "nordic,nrf-twis" are added
and the one for "nordic,nrf-i2s" is renamed to "nordic,nrf-twi",
common fields for all these bindings are extracted to a shared file
* dts/arm/nordic/
"compatible" properties in i2cX nodes are updated (when there is no
choice as only one type of TWI peripheral is available) or replaced
with a comment pointing out that the proper type of peripheral needs
to be picked at some upper layer
* drivers/i2c/
both flavors of i2c_nrfx drivers are updated with the new names of
macros generated from dts
* boards/
all i2cX nodes in dts files for boards equipped with an nRF chip are
updated with the proper "compatible" property, according to the type
of TWI peripheral that is currently selected for the board by the
corresponding Kconfig choice option (I2C_x_NRF_TWI*)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the device tree to assign the correct peripheral clock to each
UART/USART/LEUART. Previously, the clock identifier was determined
through the sequence number of the instantiated UART. This meant
configuring all UARTs when only one of the later UARTs was required.
Signed-off-by: Oane Kingma <o.kingma@interay.com>
This adds support for Kinestis K22
Co-authored-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Co-authored-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Co-authored-by: Tom Burdick <thomas.burdick@gmail.com>
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick
as system clock. It is necessary to use this timer for power
management support, so that the system can exit from deep sleep upon
expiry of timeouts.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
4 are found: 2 with a counter of 16bits and 2 with a counter of 32 bits.
However, first 32bits instance will not be exposed as it will be used by
rtos timer driver directly to implement k_busy_wait()
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The driver for STM32's independent watchdog already exists and is
compatible with the stm32wb SoC. Enable the independent watchdog
for the stm32wb series for use with this driver.
Signed-off-by: Robert Weber <robertweber95@gmail.com>
The KE1xF SoC family SIM unit differs from the other Kinetis family
SoCs. Add a unique compatiable and binding for it.
Fixes#18160
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For quite a few peripherals that are currently supported by nrfx HALs
or drivers there are no definitions of corresponding CMSIS-Core
peripheral accessing symbols that would provide their base addresses
in the proper domain (secure or non-secure), accordingly to the build
target. This commits adds devicetree nodes for these peripherals so
that their base addresses can be used in definitions of the accessing
symbols mentioned above.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Pull out the LPO fixed-clock that is part of the PMC hardware block as
its own child node of the PMC block. This is because the PMC could have
its own driver associated with it that is seperate from the LPO clk.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Update the ADC bindings to include #io-channel-cells and update the
related dts files to set #io-channel-cells.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
'interrupt-parent' should contain just the phandle of the node
interrupts are sent to.
This node (gic: interrupt-controller@f9010000) doesn't generate any
interrupts, so the 'interrupt-parent' value is never used (this is why
it wasn't caught). It'll give an error later with 'interrupt-parent'
declared as 'type: phandle' in bindings though.
Don't know what was intended. Just remove the 0.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
SPI3 clock info were missing and following macros were
not generated:
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BITS
- DT_ST_STM32_SPI_FIFO_40003C00_CLOCK_BUS
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Remove unused "system-clock-frequency" property, we don't have this
defined in various bindings and thus aren't using it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use clock specified in the device tree for obtaining the source clock
frequency for the pwm_mcux_ftm driver instead of relying on having an
NXP Kinetis MCG clock available in all SoCs supporting FlexTimer (FTM)
modules.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
NRF_UICR needs to be defined for nRF9160 SoC in
nrfx_config_nrf9160.h, because it is not defined
in nrfx/hal/mdk/nrf9160.h (as it is a Secure-only
peripheral).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With the new DT checks the dts bindings for "nxp,flexpwm" and
"nxp,imx-pwm" had old conventions that we now treat as build errors.
Additionally fix the number of #pwm-cells for "nxp,imx-pwm" to be 1.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
i.MX RT10XX processors have four eFlexPWM modules, each containing
four 2-channels PWM submodules.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The true mmio-sram nodes should not have had a 'device_type' property.
Remove it from the cases that we clearly know are SRAM.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These are not declared in dts/bindings/arm/nxp,kinetis-sim.yaml and do
not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
A minor spelling fix in an inline comment in
both nRF9160 Secure and Non-Secure .dtsi headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
These are not declared in any binding and do not generate any output.
Trying to get rid of properties that appear on device tree nodes but
aren't declared in bindings.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Fix the following dtc warning:
mimxrt1064_evk.dts.pre.tmp:78.31-85.5: Warning (spi_bus_bridge):
/soc/flexspi1@402a4000: node name for SPI buses should be 'spi'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Several aliases were added to nrf9160[ns].dtsi files solely for
the purpose of getting base addresses of certain hardware modules
via DT_ macros generated for these aliases.
Since for one-instance modules the same can be now achieved with
standard DT_INST_0_* macros, there is no need to keep these aliases.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
pinmux: Add the relevant definition of the spi3 pin
dts: Fix a bug, spi3 does not have a label
soc: Supplement spi3 related definition
Signed-off-by: Findlay Feng <i@fengch.me>
stm32f429.dtsi wrongly introduced i2s nodes 4, 5 and 6.
Remove them as actually only i2s nodes 2 and 3 are supported on
these socs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The property is required on all SPI clients, but was missing from
several devicetree nodes. Set it, using the capitalized version of the
node alias when present, with "jedec,spi-nor#0" as the fallback.
Closes#17662
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Have the SoC dtsi files for microchip mark the devices (uart & i2c) as
disabled by default and let the board dts files enable which one's they
need/use (which is what's happening already).
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
spi-max-frequency is marked as required in
dts/bindings/mtd/jedec,spi-nor.yaml.
I took the value from the datasheets (133 MHz for all), and guessed that
a dummy entry is fine for QEMU.
Fixes some errors in
https://github.com/zephyrproject-rtos/zephyr/issues/17532.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
There doesn't seem to be any use of the virtualcom device in the code,
so lets remove it from the dts as it describes itself as a usb device
controller which it is not.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds a fixed clock node (representing clock driving
system bus). The added node is then referenced by peripherals requiring
information about driving clock frequency.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit adds 'clock-frequency' property to the cpu nodes.
The clock frequency specified in the added property is used
during platform configuration. Examples:
- The SWO logger uses clock frequency to configure SWO output.
- Plenty of platforms need CPU clock specified for their HAL.
- Most of devices with USB needs information about CPU clock
in order to configure USB clock source.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This patch populates "clocks" property in stm32 usb nodes
for clock related usb configuration code of each dtsi files
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The spi-nor flash nodes require a jedec-id property as per the binding.
We add the jedec-id's as best we can determine based on the data sheets
for the various flash modules on these boards.
However these id's should be validated by actually reading the value to
ensure they are correct.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix USB phy node for stm32l432 and stm32l452, which contain
a USB controller and not a OTG FS controller.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
1) dts/bindings/mmc/mmc.yaml: specifies common mmc.
2) dts/bindings/mmc/nxp,imx-usdhc.yaml: specifies
nxp usdhc module which inherits mmc.
3) dts/arm/nxp/nxp_rt.dtsi: usdhc support on RT chip.
4) boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts:
usdhc slot support on mimxrt1050_evk board.
Signed-off-by: Jun Yang <jun.yang@nxp.com>
A number of minor issues with the 'fixed-clock' support:
* Fix the #clock-cells to be 0
* Fix nxp_ke1xf.dtsi to set #clock-cells 0 and the clock reference to
only be a phandle.
* Fix the generation script to only generate what it should for a
'fixed-clock'
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add clock support for STM32G0X SoC series.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This patch adds support for the STM32G071xx
from STMicroelectronics.
Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Added support for the STM32L496XE series with 512KB internal flash and
256KB SRAM of contiguous addresses.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
The DT spec. only has "okay" and not "ok". The Linux kernel has around
12k "okay"s and 300 "ok"s.
The scripts/dts scripts only check for "disabled", so should be safe re.
those at least.
The replacement was done with
git ls-files | xargs sed -i 's/status\s*=\s*"ok"/status = "okay"/'
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds counter driver based on RTCC module for SiLabs Gecko
SoCs.
Tested with SLWSTK6061A / BRD4250B wireless starter kit.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sram2a and sram2b where defined in the prospect of defining
HCI shared memory sections from device tree.
Remove them, since this is not the case anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This adds support for the basic timer counter (TC) found on SAM0
series parts. This driver only supports running the counter
in 32 bit wide mode. Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.
Tested with tests/drivers/counter/counter_basic_api on SAMD21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add support for the Low Power Inter-Integrated Circuit (LPI2C)
controllers found in the NXP Kinetis KE1xF SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The node name for device_id was device_id@0 it should be
device_id@80a00c to reflect the first register region
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM SysTick peripheral is optional in Cortex-M0 MCUs,
so we delete the respective dts node when the peripheral
is not present.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Atmel SAM D series SoC variants (present in the tree) all have
an ARM Cortex-M0+ core, not a Cortex-M0, so we correct this in
the .dtsi header.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of
MPU regions may vary based on the implementation. This commit
adds a DTS node for the ARM MPU peripheral in the device tree
of Cortex-M7 SoCs and updates the fixup files, so we may extract
the number of MPU regions at build time. SoCs:
- nxp_rt
- same70
- stm32f7
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a DTS node for the ARM MPU peripheral in the
device tree of ARMv8-M SoCs (for the secure and the non-secure
DTS descriptions) and updates the fixup files. SoCs:
- nrf9160
- musca_a
- musca_b1
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding missing erase-block-size entries for the flash-controller
nodes in the nrf52810 and nrf52811 .dtsi files.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move flash-controller and SRAM node definitions under SoC node.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Reduced Kconfig for counter with nRF TIMER and RTC. Added overlays
for TIMER and RTC configuration in the counter test.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
This commit adds basic support for nrf52811 in the arch SoC, dts
and nrfx folders.
The nRF52811 is a Bluetooth 5.1 Direction Finding SoC with comprehensive
protocol support.
The nRF52811 SoC is capable of the latest features of Bluetooth 5.1,
the most prominent being Direction Finding.
The radio in the nRF52811 SoC has comprehensive protocol capabilities,
including Bluetooth 5.1 Directing Finding, all Bluetooth 5 features,
802.15.4, Thread, Zigbee, ANT and 2.4 GHz proprietary.
It has 4 dBm TX power and has been optimized to offer the best RX
sensitivity of all SoCs in the nRF52 series.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
add usbd1 definition to rt dts file,
set EHCI controller config default value in rt1050 default config file,
add EHCI controller driver MACROs to dts_fixup.h,
initialize EHCI clock in rt soc.c
add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Dts Nodes for all the GPIO portswere defined. In addition,
a new binding file was created for the gpio driver.
Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
Expose MEC1501 5 I2C/SMB controllers
Add Microchip specific I2C device tree properties
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
All series of stm32 have at least one ADC instance and this commit adds
one ADC node to the root dts file of each soc, and also adds fixing up
mappings to them.
Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This adds interrupt support to the SAM0 GPIO driver. This is heavily
inspired by @nzmichaelh work in #5715. The primary difference
from that implementation is that here the External Interrupt
Controller (EIC) is separated out into an interrupt controller driver
that is less tightly coupled to the GPIO API. Instead it implements
more of a conversion from the EIC's own odd multiplexing to a more
traditional port and pin mask IRQ-like callback. Unfortunately,
through the EIC on the SAMD2x are relatively well behaved
in terms of pin to EIC line mappings, other chips that share the
peripheral interface are not. So the EIC driver implements a
per-line lookup to the pin and port pair using definitions extracted
from the ASF headers.
The EIC driver still makes some assumptions about how it will be used:
mostly it assumes exactly one callback per port. This should be fine
as the only intended user is the GPIO driver itself.
This has been tested with some simple programs and with
tests/drivers/gpio/gpio_basic_api on a SAMD21 breakout and an
adafruit_trinket_m0 board.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds a SERCOM I2C driver for SAM0 series chips.
Tested with a SAMD21 chip on a SSD1306 display and a MLX90393
sensor. Only compile tested for SAMD20 and SAMR21.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Add initial support for the TI CC13x2 / CC26x2 series with the CC2652R
and CC1352R SoCs. The UART and GPIO peripherals are supported. Drivers
use the driverlib HAL from the TI CC13x2 / CC26x2 SDK.
Signed-off-by: Brett Witherspoon <spoonb@cdspooner.com>
Implementation of pinmux for the stm32mp157c_dk2 board.
Some UART pin mux definition has been added (mainly for
UART console and UART/SPI Arduino shield support).
This can be completed with pin mux for other stm32mp157c
UART.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Add support for stm32mp1 basic UART API with Zephyr.
UART Console and UART shell are also supported.
Async UART API and USART support is to be done.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Move SERCOM peripherals to use the raw defines generated from DTS
parsing. This adds aliases to the DTS so that the SERCOM number
can still be used for clocking and pinmux.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This adds support for the SAM0 DMA Controller (DMAC). Chained
transfer are not currently implemented.
Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels. Also tested
with a trivial program that did memory->serial.
Signed-off-by: Michael Hope <mlhx@google.com>
[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupts are configured in
direct mode.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233
radio connected internally via SPI.
The AT86RF233 is not yet supprted by Zephyr at this point.
This code is very much copy & paste from atmel_sam0/samd21
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Add USART1 and LPUART1 nodes on stm32wb series.
Only these 2 ones are available for now on this series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add driver support for Atmel SAM0 device ID, which is 16-bytes long.
The device ID can simply be read from memory at a known location, but
the location is only described in the data sheet, not in ASF.
For SAMD2x it's 0x0080A00C, 0x0080A040, 0x0080A044 & 0x0080A048.
For SAMD5x it's 0x008061FC, 0x00806010, 0x00806014 & 0x00806018.
This adds a new property to the device tree to define the device ID
registers for this SoC family.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
