The interrupts generated by the generic timer behave in
a level-sensitive manner. Change the DT to reflect the same.
Fixes: #25585
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
In aarch64 DTs, priority and flags cells have been swapped,
fix the same.
Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
The flash at 0 is a cfi-flash and its 2 banks each that are 64M.
Update qemu-virt-a53.dtsi to reflect the proper flash config, however we
comment out the second bank of flash for now because zephyr,flash can
only handle one value in the reg property.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The shared irq support isn't needed in this driver. We just need to
deal with the fact that some SoCs have only a single interrupt line and
some have three interrupts. We can just ifdef that based on
DT_NUM_IRQS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add a fixed clock to the qemu-virt-a53.dtsi to match how the musca dts
files work so we get the clock DT info in the same way in the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable the shared IRQ for the UART line and enable the remaining tasks
that depends on a separated declaration of the TX/RX/Err/... IRQs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
