michaelh/zephyr
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Author SHA1 Message Date
Abhishek Shah f156057b20 dts: arm: Fix incorrect interrupt cells order 
In aarch64 DTs, priority and flags cells have been swapped,
fix the same.

Correct interrupt property per the GIC binding document
looks like:
interrupts = <irq_type irq_num irq_flags irq_priority>;

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
 2020-05-21 13:56:00 +02:00
Arjun Jyothi d18ae2e9fb soc: arm: Add Broadcom Viper SoC support 
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.

Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
 2020-05-08 10:46:23 +02:00