Commit graph

22 commits

Author SHA1 Message Date
Andrew Boie a9670ab5cf boards: centralize QEMU icount management
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-24 20:28:36 -04:00
Wentong Wu 0b2e633ce3 boards: remove the existing qemu icount configuration
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Stephanos Ioannidis a426175e00 boards: qemu_cortex_r5: Remove ignore tags for working tests
While the Cortex-R arch port does not currently support memory
protection and userspace, the `memory_protection` and `userspace` test
tags should not be ignored because doing so can unintentionally disable
other relevant tests.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-15 15:49:27 +02:00
Stephanos Ioannidis 716397411b boards: qemu_cortex_r5: Fix memory size
This commit fixes the incorrect memory (FLASH and SRAM) size
specification in the device tree and the board test yaml files.

The `qemu_cortex_r5` board (using `fdt-single_arch-zcu102-arm.dtb` FDT)
has 64MiB RAM at the address 0 and 32MiB QSPI flash at 0xc0000000.

QEMU `info mtree`:

0000000000000000-ffffffffffffffff (prio 0, i/o): memory@00000000
  0000000000000000-000000000002ffff (prio 0, ram): ddr_bank1_1@0x0
  0000000000030000-000000000003ffff (prio 0, ram): ddr_bank1_2@0x30000
  0000000000040000-0000000003ffffff (prio 0, ram): ddr_bank1_3@0x40000

00000000c0000000-00000000c1ffffff (prio 0, i/o): lqspi

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-14 09:44:27 +02:00
Stephanos Ioannidis 19965f8173 cmake: qemu: Support delayed expansion of QEMU_KERNEL_OPTION
This commit allows the `QEMU_KERNEL_OPTION` variable, which can be
overridden by the `board.cmake`, to contain references to the variables
that are not available at the time of `board.cmake` inclusion, by
expanding its escpaed variable references in `cmake/emu/qemu.cmake`
which is included nearby the end of the root `CMakeLists.txt`.

With this change, the `board.cmake` can escape variable references as
follows and allow them to be expanded later:

set(QEMU_KERNEL_OPTION "-device;loader,file=\$<TARGET_FILE:$\{...}>")

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-02 09:22:38 +02:00
Stephanos Ioannidis 95bdbe35bd boards: qemu_cortex_r5: Remove ignore tags for working tests
This commit removes the ignore tags for the tests that work after the
changes in the PR #23636.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-04-02 09:22:38 +02:00
Stephanos Ioannidis fc941d583e drivers: timer: xlnx_psttc_timer: Implement tickless support
This commit reworks the Xilinx TTC timer driver to use the "match" mode
instead of the "interval" mode which counts up to the specified value
and resets to zero.

Using the "match" mode ensures that the timer keeps counting even after
an interrupt is triggered, and facilitates the tickless mode support
implementation.

This also allows `z_timer_cycle_get_32` to return the correct cycle
count when interrupt is locked; thereby, fixing the k_busy_wait hang
issue.

Note that the TTC "match" mode emulation (and tickless timer operation)
is only stable when the QEMU icount mode is enabled.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-21 14:20:17 -04:00
Stephanos Ioannidis 1038e4d225 boards: qemu_cortex_r5: Enable QEMU icount emulation
This commit enables the QEMU icount emulation mode for improved timing
stability.

In normal emulation mode (without icount), the emulation timing of the
TTC system timer is particularly unstable and this results in a high CI
failure rate.

For more details, refer to the issues #14173 and #22904.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-21 14:20:17 -04:00
Stephanos Ioannidis fa19193898 boards: qemu_cortex_r5: Add board documentation
This commit adds the board documentation to the qemu_cortex_r5
platform.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-02-28 09:55:39 +02:00
Stephanos Ioannidis 89132fe8bd boards: qemu_cortex_r5: Remove ignore tags for working tests
This commit removes the ignore tags for the tests that work after the
changes in the PR #22037.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-02-11 08:03:37 -08:00
Kumar Gala 1f0089ff45 boards: qemu_cortex_r5: Reduce memory footprint when running
When running in qemu we utilize fdt-single_arch-zcu102-arm.dtb to
configure qemu.  The current dtb requests just under 2G of memory in the
simulation, but we don't really need this and it impacts running on low
memory VMs.

So remove DDR ddr_bank2 and reduce ddr_bank1_3 from 1G - 256K to
128M - 256K in size.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-02-08 08:31:48 -05:00
Ulf Magnusson c5839f834b kconfig: Remove assignments to CONFIG_<arch> syms and hide them
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.

CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.

Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:

1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
   turn the CONFIG_<arch> symbols into invisible
   (promptless/nonconfigurable) symbols instead.

   Getting rid of the choice allows the symbols to be 'select'ed (choice
   symbols don't support 'select').

2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
   This makes sense since you know the architecture if you know the SoC.

   Put the select on the SOC_* symbol instead for boards that don't have
   a SOC_SERIES_*.

3. Remove all assignments to CONFIG_<arch> symbols. The assignments
   would generate errors now, since the symbols are promptless.

The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.

See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.

This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-08 00:50:08 -06:00
Kumar Gala ca09a7bf07 boards: qemu_cortex_r5: remove CI workaround
Now that we have SDK 0.11.0 as default, we don't need workaround for
finding qemu.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-01-30 14:23:31 -06:00
Stephanos Ioannidis 1c9942461d boards: qemu_cortex_r5: Remove ignore tags for working tests
This commit removes the ignore tags for the tests that work after the
changes in the PR #20267.

In the future, this ignored testing tag list will be further reduced
as critical bugs for the qemu_cortex_r5 platform are addressed
(see #20217).

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Stephanos Ioannidis 09ee834b4c soc: arm: xilinx_zynqmp: Refactor for multi-arch support.
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU"
cores.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within the same project, the RPU and APU should be
considered separate platforms and handled accordingly.

This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol
indicating that Xilinx ZynqMP SoC is used, and adds a new symbol,
SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform.

When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU
symbol should be added and used to conditionally handle APU-specific
code.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Stephanos Ioannidis 8a29685a25 dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately.
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.

Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.

This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).

When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-07 17:17:12 +01:00
Stephanos Ioannidis 7aa01ff0b0 boards: qemu_cortex_r5: Remove ignored tags for working tests.
This commit removes any ignored testing tags for working tests.

In the future, this ignored testing tag list will be further reduced
as critical bugs for the qemu_cortex_r5 platform are addressed
(see #20217).

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-18 22:11:25 +01:00
Stephanos Ioannidis 59cb2acd9e boards: qemu_cortex_r5: Add a temporary hack to support CI testing.
This commit adds a temporary hack to support CI testing of the
qemu_cortex_r5 platform.

The Xilinx QEMU, required to run the tests for this platform, is
currently not available in the default SDK for CI (version 0.10.3) and
attempting to run any tests with the AArch64 QEMU included in this SDK
will cause failures (see #20217).

Since the latest SDK (version 0.11.0-alpha-8) has been added to the CI
image to allow initial testing, this hack automatically detects this
and uses the Xilinx QEMU for testing the qemu_cortex_r5 platform.

When the Zephyr SDK 0.11.0 is available as the default SDK for CI in
the future, this commit should be reverted.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-18 22:11:25 +01:00
Stephanos Ioannidis f36b39a713 boards: arm: qemu_cortex_r5: Use arm-generic-fdt machine type.
This commit modifies the 'qemu_cortex_r5' board qemu emulation to use
the arm-generic-fdt machine with the Xilinx-provided zcu102 device tree
instead of the hard-coded xlnx-zcu102 machine, which is very primitive
and cannot properly emulate the Cortex-R5 RPU of ZynqMP.

The QEMU zcu102 FDT (fdt-single_arch-zcu102-arm.dtb) in this commit was
generated from the v2019.2 release of the Xilinx/qemu-devicetrees.

Zephyr SDK version 0.11 Alpha 4 or above is required to use this, as
arm-generic-fdt is supported only by the Xilinx QEMU fork which was
added to the Zephyr SDK in the version 0.11 Alpha 4.

For more details, refer to the issue #20217.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-12-18 22:11:25 +01:00
Ulf Magnusson bd6e04411e kconfig: Clean up header comments and make them consistent
Use this short header style in all Kconfig files:

    # <description>

    # <copyright>
    # <license>

    ...

Also change all <description>s from

    # Kconfig[.extension] - Foo-related options

to just

    # Foo-related options

It's clear enough that it's about Kconfig.

The <description> cleanup was done with this command, along with some
manual cleanup (big letter at the start, etc.)

    git ls-files '*Kconfig*' | \
        xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /'

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-04 17:31:27 -05:00
Anas Nashif 32a9435ea4 tests: tracing: add tests for tracing features
Mostly build tests now, will be extended to verify CTF output once we
have this feature in sanitycheck.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-09-27 14:42:22 -04:00
Bradley Bolen 6dd94127ca boards: qemu_cortex_r5: Add qemu test board for the Cortex-R series
This adds a qemu test board using the Xilinx ZynqMP SoC.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-08-09 22:50:50 +02:00