Remove soc/arm/st_stm32/stm32YY/flash_registers.h files.
Change register accesses in stm32 flash drivers to use FLASH_TypeDef
from modules/hal/stm32/stm32cube/stm32YYxx/soc/stm32xxxxxx.h.
Fixes#16235
Signed-off-by: Sarvesh Patkar <psarvesh314@gmail.com>
Variable pages_per_bank has been introduced to ease page erase
in dual bank configurations. This has been implemented using
FLASH_OPTR_DUALBANK definition.
It happen that this was not taking into account L4+ series that
use FLASH_OPTR_DBANK instead of FLASH_OPTR_DUALBANK. This lead
to compilation issue for this driver in case of L4+ series.
So, this patch is adding the support of FLASH_OPTR_DBANK definition.
Besides, FLASH_OPTR_DUALBANK (as FLASH_OPTR_DBANK) are actually
defining availability of an option byte to configure use of Dual
Bank. So besides of its definition, its value in flash OPTR register
should be checked to ensure Dual Bank configuration is used.
This patch is taking this into account by adding the check of this
byte. Error -ENOTSUP is returned in case Single Bank is configured
since it has not be validated yet (in case Dual Bank is possible but
not configured).
Fixes#18246 for nucleo_l4r5zi
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Up to now, the only SOC that was supported in the STM32L496 series was
STM32L496XG with flash of 1MB. With the recent support of STM32L496XE,
this implementation is not correct. This patch adds support for the
other SOCs that come with flashes of 512KB and 256KB.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
move flash.h to drivers/flash.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Disable the data cache before writing to Flash, in order to workaround
silicon errata 2.2.3: "Data cache might be corrupted during Flash memory
read-while-write operation". The data cache is conditionally re-enabled
once the write is completed.
This silicon bug has been encountered while stress testing the
implementation. Here are the events leading to the fault:
- Code is executing from Flash bank 1
- A write to Flash bank 2 is initiated
- The Cortex SysTick interrupt fires while waiting for Flash write
completion
In that case, the Flash controller will perform a read-while-write
operation in order to execute the ISR code. As the data cache is enabled
by default after reset, a corruption occurs due to the silicon bug,
leading to bizarre data bus faults or unaligned access faults inside
_timer_int_handler() or one of the functions called by the ISR.
Applying the workaround devised by ST fixes the problem.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
On STM32L4, flash writes operations are performed 8 bytes at a time.
Though, it is possible that *data in flash_write functions is not
aligned. To avoid issues, use UNALIGNED_GET macro to access *data.
Issue has been detected using settings subsystem on STM32WB, which has
same 8bytes write block size. The patch is extended to STM32L4 series
for same reason.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
These devices increase the page size from 2k (standard STM32L4) to 4K,
so we must account for this.
Signed-off-by: Pushpal Sidhu <psidhu.devel@gmail.com>
L4 parts have a constant page size, so just rely on the HAL defines
that provide it, along with a read to the register which contains this
SoC's total size.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This is a prep work commit for adding flash page layout support.
The internal flash APIs for STM32 on L4 and F4 are a bit
inconsistent. Some routines take a pointer to the private data, others
don't. Those that do take it as a last argument instead of a
first. Additionally, some APIs are declared in flash_stm32.h that
aren't ever used by the family-specific files.
Clean this up by making everything take a struct device*, and marking
routines static in the common driver code when possible.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
L4 write access requires 64 bits alignment
while L4 read access does not require any alignment.
To support specific check according to read/write,erase
a parameter is added to stm32_valid_range.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
L4 have 64 bits write access.
The cast to 64 bits data address in write_dword
requires 3 right shifts on i (byte index) else the
data taken are wrong for i different from 0
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
The STM32L4x SoCs embeds a slightly different embedded flash controller
from the STM32F4x SoCs.
This particular controller has the following properties :
- Up to 2 512KiB banks divided in 2KiB pages
- Flash can be accessed in any sizes
- Flash must be written in 64bit aligned 64bit double-words
The drivers/flash/flash_stm32f4x.c is refactored into a new common
drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is
created with the STM32L4x specific functions.
To ease the refactoring and keep common functions, the STM32L4x flash
headers are slightly modified to match the hardware reference naming
and solve compilation issues.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
