Commit graph

12 commits

Author SHA1 Message Date
Hake Huang 999c59c1ec dma: add error check on peripheral to peripheral
add dma direction check for dma_sam0

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2020-06-12 13:03:28 -05:00
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Kumar Gala a58777e251 drivers: dma: atmel_sam0: Convert to use devicetree macros for dma dev
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name.  We make
the assumption in the drivers that there is a single DMA controller
instance.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 00:49:32 -05:00
Stephanos Ioannidis 2a710b1372 Revert "drivers: dma: sam0: fix DMA to peripheral transfer on SAMD5x"
This reverts commit 90cc723e65.

Using `DMAC_CHCTRLA_TRIGACT_BLOCK` breaks SERCOM UART peripheral DMA
operations (DMA-based asynchronous UART transmit operation only sends
the first byte and does not proceed any further).

The `DMAC_CHCTRLA_TRIGACT_BURST` with `DMAC_CHCTRLA_BURSTLEN(0)` is a
special case utilising the "internal FIFO", according to the datasheet
(see DS60001507E; 22.6.2.8), and should always be specified for
peripheral data transfer operations.

Also it is worth noting that Atmel and other third-party drivers use
the aforementioned "internal FIFO" configuration for peripheral data
transfers as well.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-05 13:53:49 -05:00
Ioannis Glaropoulos ba6dc5bc25 drivers: dma: sam0: fix macro definition
Fix the definition of DMA_SAM0_IRQ_CONNECT
pre-processor directive, so that it calls
DT_INST_IRQ_BY_IDX macro instead of
DT_INST_IRQ_HAS_IDX macro.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-03-30 08:32:17 -05:00
Kumar Gala 28870e7a32 drivers: atmel sam0: Convert atmel sam0 drivers to new DT_INST macros
Convert older DT_INST_ macro use in atmel sam0 drivers to the new
include/devicetree.h DT_INST macro APIs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-27 11:02:57 -05:00
Benjamin Valentin 90cc723e65 drivers: dma: sam0: fix DMA to peripheral transfer on SAMD5x
We need to select TRIGACT_BLOCK for DMA to peripheral to work.

Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2019-11-05 23:29:50 +01:00
Anas Nashif 46a5d1e5cb cleanup: include/: move dma.h to drivers/dma.h
move dma.h to drivers/dma.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Derek Hageman 59786b43b3 drivers: sam0: Fix deprecated instance macro usage
During conversion in #16815 a few device tree instance macro aliases
where missed (probably due to them existing to support future SoCs
and so not currently compiled), this fixes their usage.

Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-06-24 07:21:26 -04:00
Kumar Gala a2693975d7 dts: Convert from DT_<COMPAT>_<INSTANCE>_<PROP> to DT_INST...
Change code from using now deprecated DT_<COMPAT>_<INSTANCE>_<PROP>
defines to using DT_INST_<INSTANCE>_<COMPAT>_<PROP>.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-06-14 08:02:15 -05:00
Derek Hageman 64e02021ee drivers: dma: sam0: Implement get_status API
Implement the get_status DMA API for the SAM0 DMA controller.
The busy field is set only when the selected channel is
actively transferring data (i.e. both enabled and selected by the
arbiter).  The direction field is left unset, since that
information is not normally retained by the DMA controller.

Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-05-30 17:18:44 -04:00
Michael Hope ba21de582b drivers: dma: Add SAM0 DMAC driver
This adds support for the SAM0 DMA Controller (DMAC).  Chained
transfer are not currently implemented.

Tested with tests/drivers/dma/loop_transfer and custom modifications
to that test using three parallel reloading channels.  Also tested
with a trivial program that did memory->serial.

Signed-off-by: Michael Hope <mlhx@google.com>

[hageman@inthat.cloud: Rebased and updated commit message]
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
2019-05-02 19:20:12 -05:00