Properly document the various APIs exposed by hci_driver.h.
Change-Id: Ic8daba4956e4c5d2cc6597556b55ab5221495ad7
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
There are no users of this API and no (currently) envisioned use cases
for it. Remove it for now - it can always be brought back later if
there's a need for it.
Change-Id: I6530e096e3671c844a3f7dea8856147ffc716d71
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Rename the elements of 'enum at_cmd_type' in order to follow the
name spacing. Which should have prefix of 'AT_' for each elements.
This patch also involves the renaming, corresponding handler
function of 'enum at_cmd_type' with prefix 'at_' i.e 'cmd_start' as
'at_cmd_start'.
Change-Id: I722a25954163c06e131b94042c6a18e1e3458f6e
Signed-off-by: Sathish Narasimman <sathish.narasimman@intel.com>
The idle stack already defaults to 256. The ISR stack size of 640 was
intended to make the app fit on 16k nRF51 variants and is now the
default, i.e. it doesn't need to be explicitly set anymore.
Change-Id: I8db3c080e1f84c65b27f931fa48c75bd90a2d3cd
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Rename hci_le_rand to bt_rand and make its parameter types compatible.
This also includes updating rand_get() to use size_t instead of
uint32_t & uint8_t.
Change-Id: I4d434dfbbaf339b1bc7b451d358d07a291dd0375
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The controller bt_rand() ties into the hardware which uses less memory
and is more power-efficient than using the TinyCrypt PRNG.
Change-Id: I7570d18f3e84dae3d5c2d3322b5d37cd3e8f3b6b
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Having TX buffers split into numerous pools has the downside of
increased memory consumption. This patch takes the initial step to
consolidate these pools into a single one, saving about 248 bytes of
RAM for a basic configuration.
Change-Id: I449ba18b44a9a6af68e9a2c44f19a9286eb88b14
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Uses sys_slist_get function to get node and automatically, if valid,
remove one from the list.
Change-Id: I4cee6fbb064bf9644efdb7e6771e702b1f08678a
Signed-off-by: Arkadiusz Lichwa <arkadiusz.lichwa@tieto.com>
Fixes not supported now format specifier.
Change-Id: Ia01ea3fd18acfeed6f4a3899334911dac1b76643
Signed-off-by: Arkadiusz Lichwa <arkadiusz.lichwa@tieto.com>
HTML documentation shows misaligned text that may be a bit confusing.
This issue was caused by wrong indentation. Furthermore, board specific
instructions to build the image does not include any instruction header.
This commit fixes the above described issues.
Change-Id: Ie965e09f32f46a9d69aac28c4b389084f06b31b6
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Updated the README.rst describing how to setup the document building
tools on an Ubuntu system (listing versions of tools) and how to
generate a local copy of the html documentation.
Change-Id: I4ca1a99a48709b2313c479487abf42480c5af035
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
make build process less verbose and enable 'make htmldocs' from the top
tree without a need for ZEPHYR_GCC_VARIANT to be defined.
Change-Id: I385667e3d240205913fa806b7481d5ed4e83fbc4
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was missing and all kernel objects belong to this group.
Change-Id: I3c31b168ca984b7d44cc5614a2e2bd5cc492cf50
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Running documentation scripts on the top directory shifted all links one
level dowwn and is breaking all incoming links.
Use a script to copy all RST files into the doc/ directory before
running sphinx and keep structure intact.
Jira: ZEP-1579
Change-Id: Iccff068430e2ddb29e172cd8ae920475815d199e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove the convert_to_double function and use sensor_value_to_double
from sensor.h.
Change-Id: I92ef4219057f431917f4c8e9d46d4ee2074b423b
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Remove the type field from the sensor value structure. All values will
have the type previously defined by SENSOR_VALUE_TYPE_INT_PLUS_MICRO.
This simplifies the interface, as apps will know what value type to
expect. Apps that prefer to use double values can optain them using the
sensor_value_to_double function.
Change-Id: I3588d74258030eb16c3f89d8eead13cca4606b18
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Similar to what was available with nano timers in the original kernel,
allow a user to associate opaque data with a timer.
Fix for ZEP-1558.
Change-Id: Ib8cf998b47988da27eba4ee5cd2658f90366b1e4
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I2faa823226cd76d129d2bc3db961c9b862aaf784
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Added TICK_IRQ definition for CONFIG_PULPINO_TIMER and
CONFIG_RISCV_QEMU_TIMER
skip definition of HAS_POWERSAVE_INSTRUCTION for
CONFIG_SOC_RISCV32_QEMU, since it does not provide
power saving instruction.
Otherwise, not passing sanitycheck.
Change-Id: I43a5c5112d694efdc14c5a0bcb4cafdc196d2680
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
zedboard_pulpino
1) has a 16750 uart, which is compatible with the uart_ns16550 driver.
2) make use of the pulpino timer driver
Change-Id: Ifda710fc8dea547ada05bb42e604d7cfdff284d5
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The qemu_riscv32 board makes use of:
1) the uart_riscv_qemu driver
2) the riscv_qemu_timer driver
Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
tested with blinky, button and disco apps
Change-Id: I4b520d4f3e42c97e4a723747ce4a6c67ca9f1d18
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added USED_RAM_SIZE and MAX_HEAP_SIZE definitions for
SOC_RISCV32_QEMU and SOC_RISCV32_PULPINO.
Otherwise, not passing sanitycheck
Change-Id: Ia32b12e1694dc472e9f7f9eb10c5f2e12e928c3a
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
riscv-qemu UART:
1) comprises only one register that is used to send or
receive characters in a polling fashion.
2) does not have a FIFO and is not interrupt-driven.
Change-Id: I9408f1776eba4cec4aa203a5da759ec04bcddf1f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The riscv-qemu timer driver does not implement
TICKLESS_IDLE
Change-Id: I3eeb5abb05b3f16b55ab9343c2045295b3010cfd
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The pulpino_timer driver does not implement TICKLESS_IDLE
for the time being.
Change-Id: I0cce8c8a7e203d551a924863462e6c86af4c98ff
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)
Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Default 256 bytes stack size for idle task is not enough, as
stack grows/shrinks by a multiple of 16-bytes in the
RISC-V architecture.
Increase it to 512 bytes for RISCV32 architecture
Change-Id: I8321c48e4c1a877b252ba5561f3cbdd1fe475fc7
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
added _MOVE_INSTR for RISCV32 architecture
The store instruction has a different syntax in RISC-V,
compared to the other architectures. Hence, for each
architecture, specify the entire load instruction within
the _MOVE_INSTR variable.
Change-Id: Iedc421e73411876abd8b698f7d4b46081b473d79
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Compiling Zephyr with an external riscv32 toolchain would
require the following env variables to be exported:
export ZEPHYR_GCC_VARIANT=riscv32
export RISCV32_TOOLCHAIN_PATH=/PATH/TO/TOOLCHAIN/BINARY
Change-Id: I2072ed9079a4cabd27837ab39b947bc0a0a1a8b4
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
