classname seems to be expected by some parsers, so use it in the report,
the name now has the same value, we can add some more information once
we have meaningful metadata for the testcases with more details.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This new options makes it possible to only run a subset of the tests
which will allow us to run sanitycheck on multiple hosts and merge the
results into one report. This way we do not need to worry about
selecting specific architectures to be run on a certain host.
The option accepts a string value: x/y where x is the subset and y is
the total, so if we specify --subset 1/5, we will only run the first
fifth of the total tests, --subset 5/5 would only select the last fifth.
To get consistent results, the testcase instance list is now ordered,
to avoid duplications and have full coverage.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Support for LSM6DSL accelerometer and gyroscpe sensor
with bare minimum features.
For more info on this sensor:
http://www.st.com/en/mems-and-sensors/lsm6dsl.html
Change-Id: I9b100a3e030faa8a70a5015a881025c876b81be4
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
i2c_burst_write API implementation in some driver
and generate a sequence of messages that does not allow to
communicate with LIS3MDL sensor. This commit replaces use
of i2c_burst_write with a call to i2c_write, which enables
sensor configuration.
Meanwhile, description of LIS3MDL is completed in sensor
header file.
Change-Id: Ib1b4643365f3c70b31fbfc4b0c30cff294b475a3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Support for LPS22HB Pressure and temperature sensor provided
with bare minimum features.
For more info on this sensor:
http://www.st.com/en/mems-and-sensors/lps22hb.html
Change-Id: I14992b954053094beb054d0dba7581f6e29a3e68
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The xtensa simulator can in fact simulate a variety of Xtensa SOCs.
Fixes build for alternate xt-sim_* defconfigs.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The xt-sim defconfigs were selecting CONFIG_SIMULATOR_XTENSA instead
of CONFIG_BOARD_SIMULATOR_XTENSA.
Fix defconfigs and rename to CONFIG_BOARD_XT_SIM to ease any future
confusion between these similarly named defconfigs.
CONFIG_SIMULATOR_XTENSA is automatically set by xt-sim's
Kconfig.defconfig, it doesn't need to be explicitly specified in the
defconfigs themselves.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
To better debug the flow of events into the Host, log the subevent code
whenever processing an LE Meta Event.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
XCC doesn't recognize the "I" compiler constraint but GCC does. Switch
to "i" which is understood by both.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Now that all ARM platforms have a device tree we can move selecting of
HAS_DTS up and remove any !HAS_DTS cases, as well as setting in all the
defconfigs.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add missing UARTs from the main device tree. They are declared as
disabled and can be enabled individually by each board.
Change-Id: I0ec73c59b4c3c4ee56f12ae70f2d6cdbec14fe33
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add defines and pinmux arrays to support more UARTs on STM32F4.
Change-Id: Ib06c549bdb2b3d7065554a0a6d1a3d15441b29c9
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
It is useless to include the pinmux for a peripheral if it is not
enabled in the Kconfig. This is unnecessary and it increases the size of
the binary.
Define macros that will default to void if the associated Kconfig is not
enabled.
Change-Id: I0857fcef335c75b8bb6d537fd859f93d5be4a228
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Clean-up the pinmux arrays as a preparatory work before adding more
pinmuxes.
This is achieved by the following two actions:
- Define the PAD macro to simplify the [x - 1] = y construct
- Reorder the declartions by bank / pin to make it easier to
locate a pin among a high number of other pins, while minimizing the
risk of conflict when two people add a new declaration for two
different pins
Change-Id: I1ca0cc4f48bcd8cfd35b331e9821935f5c855876
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add support for U(S)ART 4 to 10 that can be found at least on some
members of the STM32F4 family.
Change-Id: Ie870492511f885005cf023040e498bd4d800e807
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The registration of each serial port differs only by a few details.
These differences can be factorized in order to create a generic
registration macro.
This has several advantages:
- Less code
- Easier to add new ports
- Less work to add support for new STM32 families
Change-Id: I6e62a96ccbbf03c9d51bc2617db6a851ff0d83c7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary board files, pinmux and device tree in order to have a
usable debug console.
Origin: Original
Change-Id: I280320700352fd36a544c03f4e57d2eeec2449e5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add necessary Kconfig and minimal device tree in order to support
STM32F413xH variants as found on the Nucleo STM32F413 board.
Origin: Original
Change-Id: I60230c240d6acb610f16a02c62048d448476e9c5
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The bitfield determining the I/O direction already defines the pin
as either input or output, cannot be none or both at the same time
This issue was reported by Coverity
Coverity-CID: 151970
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds a new debug support script using pyOCD and configures most NXP
boards so they can use it. frdm_kw41z is the one exception because pyOCD
doesn't yet support kw41z. Tested with pyOCD v0.8.0 and the latest
DAPLink firmware for each board.
Introduces two new environment variables, PYOCD_FLASHTOOL and
PYOCD_GDBSERVER, that allow you to set custom paths to the pyOCD tools.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Not all the boards (for instance the Nuclo F412) use USART1 or USART2.
Let each board enable these USARTs when really used.
Change-Id: Idfe79c724bd7b1ab154310b4a8234b52eef2298d
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Commit 87893ddf7ad4 ("soc: stm32f429zi: rename SOC config flag") renamed
SOC_STM32F429XX to SOC_STM32F429XI but the text of the option should be
changed as well to reflect this restriction in scope.
Change-Id: I2627b59f805e73d6c8a3534e0feec71a4269c9ab
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Commit 599149dfb831 ("soc: stm32f407xg: rename SOC config flag") renamed
SOC_STM32F407XX to SOC_STM32F407XG but the text of the option should be
changed as well to reflect this restriction in scope.
Change-Id: Id03529452f5ec7d7ffee214b152c4aa555e1208a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Adds a new debug support script using Segger JLink and configures all
NXP boards so they can use it. Tested with Segger JLink GDB server
V6.14b and OpenSDA v2.1 firmware.
Change-Id: Ia1b297d9c93d21db61379e22f27ae54cda3ad461
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Rename SOC_STM32F407XX to SOC_STM32F407XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file).
Change-Id: I0afa16e86b7c99b9e685004f96beeb888f9e7568
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32F429XX to SOC_STM32F429XI to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: Id188b7703d2bce0a3ded09132ff0f205efa9c143
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The RX pin should be PA15 to use the Virtual COM port of the ST-LINK.
Also adds the missing entry in pinmux_stm32l4x.h.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This patch enables the generation of the ARM CMSDK UART base address
from the device tree.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
During introduction of LL clock_control driver on stm32f4 series,
AHB2 clock activation/deactivation case was let under stm32l4 condition
preventing activation of this clock with F4 series.
This patch fixes the issue.
Change-Id: I5e488e990d33252f491f8960fc7a798ca3416be2
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
It is possible to remove the forward declaration of l2cap_alloc_buf as
the recv pointer can be compared directly with chan pointer avoiding
using l2cap_ops directly.
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
When required Rx MTU is less than configured Rx MPS, the
resultant initial credits was 0 which prevented any L2CAP
packet to be received.
Fixed by ceiling the initial credits count in the credits
calculation.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
For all arches except ARC, enable stack sentinel and test that
some common stack violations trigger exceptions.
For ARC, use the hardware stack checking feature.
Additional testcase.ini blocks may be added to do stack bounds checking
for MMU/MPU-based stack protection schemes.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.
This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
- There's no clear need to disable frame pointers if this feature is
used, remove this directive.
- The 'top' and 'base' terms are reversed. The 'base' is the high
address of the stack. The top is the lowest address, where we cannot
push further down. Fixup member and offset names to correspond to how
these terms are used in hardware documentation.
- Use correct pointers for stack top location
- Fatal exceptions now go through _NanoFatalErrorHandler to report the
faulting ip and thread.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The initial dummy thread context used for the initial __swap to
the main thread at early kernel initialization was not marked as a dummy
thread as it ought to be.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Sometime it is observed on the Arduino 101 that when we write more than
4 bytes into TX USB Endpoint, first 4 bytes are getting repeated
(frequency of occurrence ~1/3000).
This patch does following :-
1. In sample application "cdc_acm", it adds capability to
handle partial transfer data incase data is transferred partially
if exceeds maximum data transfer size.
2. It restricts write of more than 4 bytes into TX USB Endpoint.
This is work around to avoid issue occarance.
Jira: ZEP-2074
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch amounts to a mostly complete rewrite of the k_mem_pool
allocator, which had been the source of historical complaints vs. the
one easily available in newlib. The basic design of the allocator is
unchanged (it's still a 4-way buddy allocator), but the implementation
has made different choices throughout. Major changes:
Space efficiency: The old implementation required ~2.66 bytes per
"smallest block" in overhead, plus 16 bytes per log4 "level" of the
allocation tree, plus a global tracking struct of 32 bytes and a very
surprising 12 byte overhead (in struct k_mem_block) per active
allocation on top of the returned data pointer. This new allocator
uses a simple bit array as the only per-block storage and places the
free list into the freed blocks themselves, requiring only ~1.33 bits
per smallest block, 12 bytes per level, 32 byte globally and only 4
bytes of per-allocation bookeeping. And it puts more of the generated
tree into BSS, slightly reducing binary sizes for non-trivial pool
sizes (even as the code size itself has increased a tiny bit).
IRQ safe: atomic operations on the store have been cut down to be at
most "4 bit sets and dlist operations" (i.e. a few dozen
instructions), reducing latency significantly and allowing us to lock
against interrupts cleanly from all APIs. Allocations and frees can
be done from ISRs now without limitation (well, obviously you can't
sleep, so "timeout" must be K_NO_WAIT).
Deterministic performance: there is no more "defragmentation" step
that must be manually managed. Block coalescing is done synchronously
at free time and takes constant time (strictly log4(num_levels)), as
the detection of four free "partner bits" is just a simple shift and
mask operation.
Cleaner behavior with odd sizes. The old code assumed that the
specified maximum size would be a power of four multiple of the
minimum size, making use of non-standard buffer sizes problematic.
This implementation re-aligns the sub-blocks at each level and can
handle situations wehre alignment restrictions mean fewer than 4x will
be available. If you want precise layout control, you can still
specify the sizes rigorously. It just doesn't break if you don't.
More portable: the original implementation made use of GNU assembler
macros embedded inline within C __asm__ statements. Not all
toolchains are actually backed by a GNU assembler even when the
support the GNU assembly syntax. This is pure C, albeit with some
hairy macros to expand the compile-time-computed values.
Related changes that had to be rolled into this patch for bisectability:
* The new allocator has a firm minimum block size of 8 bytes (to store
the dlist_node_t). It will "work" with smaller requested min_size
values, but obviously makes no firm promises about layout or how
many will be available. Unfortunately many of the tests were
written with very small 4-byte minimum sizes and to assume exactly
how many they could allocate. Bump the sizes to match the allocator
minimum.
* The mbox and pipes API made use of the internals of k_mem_block and
had to be ported to the new scheme. Blocks no longer store a
backpointer to the pool that allocated them (it's an integer ID in a
bitfield) , so if you want to "nullify" them you have to use the
data pointer.
* test_mbox_api had a bug were it was prematurely freeing k_mem_blocks
that it sent through the mailbox. This worked in the old allocator
because the memory wouldn't be touched when freed, but now we stuff
list pointers in there and the bug was exposed.
* Remove test_mpool_options: the options (related to defragmentation
behavior) tested no longer exist.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit creates a HTTP server library. So instead of creating
a complex HTTP server application for serving HTTP requests, the
developer can use the HTTP server API to create HTTP server
insteances. This commit also adds support for creating HTTPS servers.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
When a new UDP or TCP connection handler is to be registered,
we need to check if identical handler has already been created.
If a duplicate is found, the registering call will return -EALREADY.
The earlier code did not check this but allowed two identical
handlers to be created. The latter handler was never called in
this case.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
