An issue was seen after changes introduced in #17933.
The net_context callback was run after we checked that it
was run ok. This test failed of course in that case. Simple
solution is to k_yield() which will make sure that the
callback gets called before we continue. This works for this
test as our threads have suitably selected priorities.
There is also no need to use K_NO_WAIT here so replacing the
timeout with K_FOREVER.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The pytest.raises context manager is now returning an ExceptionInfo
whose str() doesn't contain the str() of the underlying exception
object. Take str(e.value) directly to make sure we're looking at the
exception string.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
The main change is the elimination of the bootstrapper, a design flaw
/ misfeature.
Update the documentation to be compatible with the 0.6.x releases as
well. This has to be done atomically, as there were incompatible
changes. Make use of the versionchanged and versionadded directives
to begin keeping track of how these APIs are evolving.
(Note that west 0.6.0 will remain compatible with the extension
commands in Zephyr v1.14 LTS as long as that is still alive. This
change is targeted towards Zephyr 2.0 users.)
This requires a bump in the shippable container and allows us to
simplify the west_commands test procedure.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Now that the runners package no longer depends on west, we can move
the documentation for it from the orphan west-apis.rst page to the
build-flash-debug.rst page that documents the west extension commands
which use that package.
(This is a more logical place for this information, but it was
previously not possible to put it there since we must be able to build
the documentation on a system without west installed, excepting
content in west-apis.rst. Removing the dependency means the runners
automodule directive can safely appear in build-flash-debug.rst.)
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
SPI NOR devices require that writes be performed within only one page at
a time. There is no such limitation on reads. Remove the code that
forced reads to be performed in 256-byte chunks.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The code failed to increment the address after completing a partial
write, causing writes that cross a page boundary overwrite at a page
level.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The message talks about seconds but displays ticks. Adjusting the
parameter to convert ticks to seconds then. But also adding the ticks
since it is a valuable information when testing counter devices.
Fixing small style issue (parameter indentation) as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
System clock for m4 core was set to same clock as m7 core.
This is wrong as m4 its value is actually based on clock frequency
value after D1CPRE (sys_d1cpre_ck) divided per HPRE value, 200MHz in
current case.
This also matches the max clock speed for the m4 core (200MHz)
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
cores
In order to prevent potential misconfiguration set the clock setting,
which impacts both cores, under board.defconfig file which is used
by both core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Makes the code that defines stacks, and code referencing
areas within the stack object, much clearer.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, context switching on x86 with memory protection
enabled involved walking the page tables, de-configuring all
the partitions in the outgoing thread's memory domain, and
then configuring all the partitions in the incoming thread's
domain, on a global set of page tables.
We now have a much faster design. Each thread has reserved in
its stack object a number of pages to store page directories
and page tables pertaining to the system RAM area. Each
thread also has a toplevel PDPT which is configured to use
the per-thread tables for system RAM, and the global tables
for the rest of the address space.
The result of this is on context switch, at most we just have
to update the CR3 register to the incoming thread's PDPT.
The x86_mmu_api test was making too many assumptions and has
been adjusted to work with the new design.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The current API was assuming too much, in that it expected that
arch-specific memory domain configuration is only maintained
in some global area, and updates to domains that are not currently
active have no effect.
This was true when all memory domain state was tracked in page
tables or MPU registers, but no longer works when arch-specific
memory management information is stored in thread-specific areas.
This is needed for: #13441#13074#15135
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Need to enumerate the constraints on adding a partition
to a memory domain, some may not be obvious.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These turned out to be quite useful when debugging MMU
issues, commit them to the tree. The output format is
virtually the same as gen_mmu_x86.py's verbose output.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Currently page tables have to be re-computed in
an expensive operation on context switch. Here we
reserve some room in the page tables such that
we can have per-thread page table data, which will
be much simpler to update on context switch at
the expense of memory.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Has the same effect of catching stack overflows, but
makes debugging with GDB simpler since we won't get
errors when inspecting such regions. Making these
areas non-present was more than we needed, read-only
is sufficient.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Some options like stack canaries use more stack space,
and on x86 this is not quite enough for ztest's main
thread stack to be 512 bytes.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Populate thread->stack_obj earlier in the thread initialization
process such that it is set when z_new_thread() is called.
There was nothing specific about its position, or the rest of
the code in that CONFIG_USERSPACE block, so just move it all up..
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add the serial wire JTAG configuration of the stm32f1x family.
Before gpio is initialized, you can choose to turn off the debug pin to
make the used pins available.
Signed-off-by: Findlay Feng <i@fengch.me>
It's been annoying that there was no convenient way to get back to the
documentation home page. There is a link in the breadcrumb trail at the
top of the page, but folks didn't notice that. This PR adds a
"Documentation Home" link at the top of the left-nav menu.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The sector size is 0 will pass "fs->sector_size % info.size" then start
a loop in nvs_startup() and never return. So retrun an error if the
sector size is 0.
Signed-off-by: Harry Jiang <explora26@gmail.com>
Modify mqtt_publisher sample to use mqtt_client_set_proxy().
Removed CONFIG_MQTT_LIB_SOCKS based setup.
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
Current SOCKS5 based connections in mqtt are only
TCP (nonsecure) based. To support TLS based SOCKS5
connections, new methods needs to be introduced.
Instead, removed CONFIG_MQTT_LIB_SOCKS based implementation.
And now mqtt provides an api to set proxy
(mqtt_client_set_proxy()) details. That's enough,
socket layer will take care of making connections through
proxy server.
Fixes: #17037
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
Current SOCKS5 implementation is above socket level and every
higher layer protocol or application level needs to have
SOCKS5 related changes. This solution is based on socket
setsockopt(). Application caller has to set proxy details
through setsockopt() and socket:connect() will take care
creating connection.
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
The SO_SOCKS5 socket option can be used by the application to
set the SOCKS5 proxy details. These details will be used when
connecting to peer.
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
The init addr should contain the on-air address used to establish the
connection. The dst address contains either the current RPA of the
unknown peer, or the identity address after identity information has
been exchanged.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Error codes are listed in header files and in the core spec as hex
values. Always print them in hex in debug for easier error code
checking.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The string "xx:xx:xx:xx:xx:xx (random-id)" is 30 characters including
zero termination.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The SDK version is of the form X.Y.Z. Change the cmake scripts to be
based on X.Y of the version. This allows us to easily support newer
toolchains without having to explicitly add cmake files for the version
as well as removes duplication between those files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Fix an issue where the generated identity was not permanently stored.
This resulted in being unable to reconnect after bonding when using
privacy, since a new local IRK was generated on reboot.
When settings is enabled the application is responsible for loading
identities and possible creating its own identities.
When settings_load is called and no identities has been created or found
in persistent storage a new identity will be created.
Since bt init has not been finalized bt_id_create will not make a call
to bt_settings_save_id. So we need to make sure that this identity will
be stored.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add two bindings
test-bindings/multidir.yaml
test-bindings-2/multidir.yaml
and a new test-multidir.dts with two nodes that use them.
Verify that the two bindings were found by checking the
Device.binding_path attribute for the two device nodes.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
gen_defines.py and edtlib.py were recently added in
commit 62d5741476 ("dts: Add new DTS/binding parser").
The old extract_dts_includes.py script allowed for multiple
dts bindings dirs. Let's add that functionality to the new
scripts as well.
Signed-off-by: Michael Scott <mike@foundries.io>
There are two aspects to this: CPU registers are twice as big, and the
load and store instructions must use the 'd' suffix instead of the 'w'
one. To abstract register differences, we simply use a ulong_t instead
of u32_t given that RISC-V is either ILP32 or LP64. And the relevant
lw/sw instructions are replaced by LR/SR (load/store register) that get
defined as either lw/sw or ld/sd. Finally a few constants to deal with
register offsets are also provided.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
These defines are specific to the Cortex-M. Move them to their own
header file to prepare for Cortex-R support.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
