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1000 commits

Author SHA1 Message Date
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Pete Johanson f525a4b25a usb: stm32wb: Properly lock Sem5 before initializing USB.
* AN5289 notes that Sem5 should be held before configuring
  CLK48 for USB timing.

Signed-off-by: Pete Johanson <peter@peterjohanson.com>
2020-06-02 20:11:30 +02:00
Francois Ramu 992c005ab9 soc: arm: stm32 TICKS value with LPTIM config
This is defining the SYS_CLOCK_TICKS_PER_SEC default value
depending on the LPTIM CLOCK frequency in case of LPTIMER,
to get a TICK value as a divider of the LPTIM clock source.
It gives a better result in formulas when converting
ticks to count unit.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-05-29 14:13:05 +02:00
Armand Ciejak 9e923ee713 soc: arm: cortex_m: Fix OCRAM config for i.MX RT
OCRAM is attached to the flexram controller like the DTCM.

Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
2020-05-27 16:18:26 +02:00
Armand Ciejak 8781d612d0 soc: arm: cortex_m: Improve error messages
Use a different message for flash and sram.

Signed-off-by: Armand Ciejak <armand@riedonetworks.com>
2020-05-27 16:18:26 +02:00
Martí Bolívar 6e8775ff84 devicetree: remove DT_HAS_NODE_STATUS_OKAY
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:

- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
  for macros which are equivalent to
  DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name

Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.

This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-13 18:24:42 +02:00
Stephanos Ioannidis edeed72869 soc: atmel_sam0: samd21: Fix interrupt line count
The Atmel SAM D21 SoC, according to the original Atmel datasheet
(Atmel-42181N), has 28 interrupt lines (0-27).

There have been mysterious changes in the number of interrupt lines and
on-chip peripherals in the recent Microchip datasheet releases, but
there is no explicit information available for this (e.g. PCN), so we
take the safest approach by assuming the lowest interrupt line number.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-12 17:13:11 +02:00
Karl Zhang 1a001cc94d arm: mps_an521_nonsecure: Add TFM BL2 support
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.

Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2020-05-09 16:21:51 +02:00
Parthiban Nallathambi f4adfd52cb drivers: serial: add XMC seris UART support
Add infineon XMC4 series UART support. Driver supports
only poll mode using XMCLib.

Out of 4 available UART's on SoC, only UART1 is confgired
by default in UART mode until GPIO & pinctrl support.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-05-09 14:21:44 +02:00
Parthiban Nallathambi b687d76d09 soc: arm: add infineon_xmc series support
Add infineon xmc series with XMC4500 support. XMC series comes with,
- CPU operates upto 120MHz
- 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation)
- upto 1MB flash

init: clock control & gpio is not done, so SoC initialization directly
relies on HAL. Core operating clock is stored in no_init section, which
is kept under DSRAM1. Only DSRAM1 is used until clock support. Using
PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next
revision.

Note: SystemInit cannot be consumed directly due to vector table +
HAL linker dependency.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-05-09 14:21:44 +02:00
Sandeep Tripathy a515934a4b plat: bcm_vk: core specific init
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
 be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
 This initialization can be done at 'EL3' only.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-05-09 12:23:40 +02:00
Kumar Gala c2135f8721 devicetree: DT_NODE_HAS_COMPAT_STATUS_OKAY -> DT_NODE_HAS_COMPAT_STATUS
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-08 19:37:18 -05:00
Martí Bolívar 17b8667197 dts: clean up some redundant DT checks
These are redundantly checking a node's status twice.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-08 19:37:18 -05:00
Martí Bolívar 7e0eed9235 devicetree: allow access to all nodes
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.

Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.

To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:

- emit macros for all existing nodes in gen_defines.py, regardless
  of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-08 19:37:18 -05:00
Mieszko Mierunski 8538e7133a soc: nordic: Add support for nRF52820
This commit adds basic support for nRF52820 SoC.
Changes affect introducing:
 - architecuture files (dtsi)
 - configuration of nrfx drivers
 - adaptation of inclusions based on chosen SoC

Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
2020-05-08 15:00:41 +02:00
Sahaj Sarup 351f39f9cd board: arm: Add Support For 96Boards Aerocore2
Changes:

- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4

Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.

This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2020-05-08 07:33:43 -05:00
Sahaj Sarup 161d8c0c21 arm: soc: add support for stm32f427
Add STM32F427. This is mainly aimed towards the stm32f427vi.

Changes:

- Add stm32f427 support based on previous work
done for the stm32f429.
- Rework currunt stm32f429 implimentation to now
be based on stm32f427.
- Introduce dedicated dtsi for the VI variant of both
stm32f427 and stm32f429. This is done to prevent stm32f4.dtsi
from being included twice.

Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
2020-05-08 07:33:43 -05:00
Stephanos Ioannidis 7778c22b60 soc: arm: atmel_sam: samv71: Remove ARM_MPU selection
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.

This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 11:11:59 +02:00
Stephanos Ioannidis 51a2655cca soc: arm: atmel_sam: same70: Remove ARM_MPU selection
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.

This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-08 11:11:59 +02:00
Arjun Jyothi d18ae2e9fb soc: arm: Add Broadcom Viper SoC support
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.

Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-05-08 10:46:23 +02:00
Erwan Gouriou f81c5547f2 boards: nucleo_l552ze_q: Set system clock to 110MHz
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou 1d3c1f8d2e drivers/serial: Add support for stm32l5 soc
Add serial support for STM32L5 serial driver and instances

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou cdd5856167 driver/gpio: stm32: Add STM32L5 support
Add basic GPIO support. Regarding interface with EXTI,
STM32L5 is similar to STM32G0.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou 1f054a7b31 drivers/exti: stm32: Add support for STM32L5 series
Add support for stm32l5 socs on stm32 external interrupts driver

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou f258199595 drivers/clock_control: Add clock_control on STM32L5 series
Add clock_control driver for STM32L5.
It's based on L4/WB driver since it is similar IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Erwan Gouriou 3057d801c7 soc/arm/st_stm32: Add stm32l5 series soc support
This provides basic stm32l5 series SoC support.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-05-08 00:34:34 -05:00
Andrei Gansari 0b4cfbebe8 soc: lpc55xxx RNG definiton
Definiton for LPC55xxx family RNG device.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-07 23:25:31 -05:00
Francois Ramu dc04ce84a4 soc: arm: stm32wb55x series enabling dma and dmamux
This patch defines the dma feature for the stm32wbXX
and the dmamux feature for the stm32wb55x
soc series from STMicroelectronics

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2020-05-07 23:03:20 -05:00
Gerard Marull-Paretas cfebfc188e drivers: adc: stm32: add support for H7 series
Add support for ADC on H7 series. Note that ADC1 and ADC2 share the same
register set, so it is added as "adc1_2".

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-05-07 23:01:59 -05:00
Kumar Gala 10a5c438fc soc: arm: atmel_sam: Remove soc_pinmap.h
All pin configuration for ATMEL SAM SoC come from devicetree so we can
now remove the soc_pinmap.h header files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 22:24:58 -05:00
Kumar Gala 6ae8664889 drivers: i2s: i2s_sam_ssc: Convert to devicetree
Convert i2s_sam_ssc driver to utilize devicetree.  We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree.  We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 22:24:58 -05:00
Richard Osterloh 6b41ce5b67 soc: stm32g4: Fix typo in include filename for wwdg
Due to a typo compiling the WWDG on the g4 family does not
work. This adds the correct include filename.

Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
2020-05-07 17:24:20 -05:00
Andrei Gansari 3cc0aa7c62 soc: lpc devices spi clock speed increase
High Speed Flexcomm device that handles high speed SPI transfer are
mapped to the same High Frequency clock that the ARM core uses.
This allows for higher frequency SPI traffic.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-05-07 12:47:34 -05:00
Carles Cufi da5aa23af3 soc: ti_simplelink: Port to the new timeout API
Port the usage of the timeouts to the new timeout API, in order to be
able to deselect the legacy timeout option.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2020-05-07 11:01:55 +02:00
Kumar Gala a58777e251 drivers: dma: atmel_sam0: Convert to use devicetree macros for dma dev
Convert to using DT_INST_LABEL() in the dma driver and convert dma users
to use the DMA property macros to get the dma controller name.  We make
the assumption in the drivers that there is a single DMA controller
instance.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-07 00:49:32 -05:00
Martí Bolívar edeb555a8b devicetree: fix a couple of late-breaking DT_HAS_NODE()
Replace with DT_HAS_NODE_STATUS_OKAY.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-06 13:59:27 -05:00
Alex Porosanu 7187d624a7 soc: kinetis: add support for TPM PWM module
Some Kinetis SoCs have an instance of the the TPM module
that can be used for PWM control. As such, add the necessary
configurations to enable it on the SoCs that support it, as well as
enable the clock for the module to function.

In this case, the enablement is done only for the KW41Z SoCs,
but there are other SoCs that support it, f.i. KW38Z

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
2020-05-06 11:33:37 -05:00
Armando Visconti 5097ce6e35 soc: arm: stm32: Enable I2S_STM32 in the common part
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2020-05-06 10:33:07 -05:00
Kumar Gala fdd85d5ad7 dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear.  As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-06 05:25:41 -05:00
Kumar Gala 979904b6af soc: arm: nxp_lpc: Convert from Kconfig to DT_NODELABEL
As we phase out per instance Kconfig symbols convert to utilize
DT_NODELABEL for SPI and I2C instances instead.

Also updated comments to change from FLEXCOMM8 to HSLSPI.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-05 08:57:45 -05:00
Kumar Gala 463bce59e4 dts: Remove dts_fixup.h
Remove all remaining dts_fixup.h as all defines in the files are no
longer utilized.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-05 15:46:50 +02:00
Kumar Gala 26c2c010ee dts: Remove DT_ADC_{0..2}_NAME references from dts_fixup.h
Remove DT_ADC_{0..2}_NAME from dts_fixup.h, if this casues the
dts_fixup.h file to be empty we remove the file as well.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-04 14:00:44 -05:00
Kumar Gala dff8715615 drivers: ethernet: sam_gmac: rework pin config
Reworked sam_gmac driver to get pin ctrl/mux configuration information
from the device tree instead of via Kconfig and defines in soc_pinmap.h

We remove defines from soc_pinmap.h that are no longer needed due to
getting all that information from devicetree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-04 11:32:10 -05:00
Stephanos Ioannidis 7efa38583a soc: arm: same54: Add MPU selection
This commit adds the missing `CPU_HAS_ARM_MPU` selection for the Atmel
SAM E54 series SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Stephanos Ioannidis 319227de20 soc: arm: same53: Add MPU selection
This commit adds the missing `CPU_HAS_ARM_MPU` selection for the Atmel
SAM E53 series SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Stephanos Ioannidis e4c83ddcf4 soc: arm: same51: Add MPU selection
This commit adds the missing `CPU_HAS_ARM_MPU` selection for the Atmel
SAM E51 series SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Stephanos Ioannidis 2c416a9d50 soc: arm: samd51: Add MPU selection
This commit adds the missing `CPU_HAS_ARM_MPU` selection for the Atmel
SAM D51 series SoC.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Stephanos Ioannidis 4d59f4af60 soc: arm: atmel_sam: Add devicetree.h inclusion in soc.h
This commit adds the `devicetree.h` header inclusion in the Atmel SAM-
family SoC header files, as required by the ARM SoC conventions.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Stephanos Ioannidis d1e0bd2c5d soc: arm: atmel_sam0: Add devicetree.h inclusion in soc.h
This commit adds the `devicetree.h` header inclusion in the Atmel SAM0-
family SoC header files, as required by the ARM SoC conventions.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-05-04 17:14:35 +02:00
Henrik Brix Andersen 09367b7053 soc: nxp: k6x: enable DAC driver
Enable the driver for the Kinetis Digital-to-Analog (DAC) modules
present in the NXP Kinetis K6x SoC series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-05-01 12:35:50 -05:00