In order to avoid pin configuration conflicts between peripherals,
add CONFIG_ADC flag to for each adc pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_PWM flag to for each pwm pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_I2C flag to for each i2c pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SPI flag to for each spi pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to avoid pin configuration conflicts between peripherals,
add CONFIG_SERIAL flag to for each serial pinmux configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit updates the documentation so that it no longer requires
ZEPHYR_SDK_INSTALL_DIR and ZEPHYR_TOOLCHAIN_VARIANT to be used when
using the Zephyr SDK.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
test_testsuite_class.py: Add testcases for add_testcases function
of testsuite class in sanitycheck.
test_data/testcases/tests & /samples : Testcase root directory
to add all the testcases & to test add_testcases function.
conftest.py: Module for common pytest fixtures, also used for
passing data from one testcase to another.
Note: conftest.py has a class_testsuite fixture where board_root is
defined as the directory which will be added in a separate PR.
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
The device structure definition in the code has drifted from the
displayed version in the documentation. Update the documentation to
match.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
The underlying structure is not suitable for use in API invoked from
user threads for the reasons explained in the edit.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Extend the provided template with annotated examples of API based on
whether the functions must be invokable from user mode threads, since
there are currently no in-tree examples of the specific techniques
required.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Kernel objects were being directly accessed without previously
calling k_thread_access_grant().
This change allows each test that requires an asynchronous
event to send it to a common work queue with correct
permissions.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
There was a possible race condition between sock_is_nonblock()
and k_sem_take() in spair_read() and spair_write() that was
mitigated.
Also clarified some of the conditional branching in those
functions.
Signed-off-by: Christopher Friedt <chrisfriedt@gmail.com>
According to below rule which's from DWARF5 sepc, if the
attribute can't be founded in given DIE, check more entry
associated by DW_AT_abstract_origin.
For the purposes of determining whether a debugging information
entry has a particular attribute (such as DW_AT_name), if
debugging information entry A has a DW_AT_specification or
DW_AT_abstract_origin attribute pointing to another debugging
information entry B, any attributes of B are considered to be
part of A.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
On some STM32 boards : nucleo_wb55rg, nucleo_l152re
the test lasts longer than defaut 60sec timeout.
Increase timeout to 120 sec.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.
Fixes#25337
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This makes the up_squared board default to x86_64.
This also adds a new board, up_squared_32, for when 32-bit
is desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
UARTs and I2C controllers are accessed through MMIO and
these regions need to be added to MMU for proper access.
This also enable MMU for Apollo Lake by default since
serial console is now usable.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Given that the UP Squared has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SoCs usually have devices that are accessed through MMIO.
This requires the corresponding regions to be marked readable
and writable in the MMU or else accesses will result in page
faults.
This adds a function which can be implemented in the SoC code to
specify those pages to be added to MMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The integers used for pointer calculation were u32_t.
Change them to uintptr_t to be compatible with 64-bit.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This file consists only of an array of per-CPU IOAPIC ID's that
overrides the weak symbol defined by the architecture.
The IOAPIC IDs are only used when targetting a startup IPI for the
auxiliary right now, but the IDs are the IDs and represent hardware
truth. They should be correct even if unused.
Using the wrong ones also breaks the tests/kernel/mp test, which calls
arch_start_cpu() when not in SMP mode as a deliberate unit test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This test works by starting a bunch of poll events, dropping the test
thread priority, calling k_poll(), and assuming that all the timeouts
that fired woke up high priority threads and thus ran before k_poll()
could return. But that isn't true if you have another CPU that can
run the low priority thread while the last high priority thread
finishes up!
This just isn't SMP-correct. Mark 1cpu.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When PCIe is enabled for UART, the port address is probed during
initialization and is written back into the device config struct.
However, the device config struct is supposed to be const and
read only. This results in page faults when MMU is enabled as
the struct cannot be written into. So fix this by storing port
address in device data struct if a particular UART instance is
of PCIE.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The init function returns successful even if the first
configuration function call fails. This may leave
a non-usable UART to be discoverable with
device_get_binding() which will definitely result
in lots of head scratching. So change the init function
to return properly.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the calls to read_timer_{start,end}_of_tick_handler()
to mark the start and end of ISR which will be used to display
the time spent in ISR with benchmarking tests.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Clarify what happens when the period parameter is zero or equal
to the period.
Signed-off-by: Alexander Wachter <alexander.wachter@leica-geosystems.com>
IRQ_CONNECT() can only be called at one location to connect the irq for
CPE0. This commit modifies the driver to call into the HwiP layer in TI
HAL so that TI's RF driver can do the same when connecting the irq.
Fixes#25216
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
New update of hal_ti requires DeviceFamily_CC13X2/DeviceFamily_CC26X2
to be defined in order to include the rfc.h header.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Building a couple more files from the SimpleLink SDK in order to support
the ieee8021504 driver for CC13xx/CC26xx.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
Though there were issues with this sample before e959386bd2 ("samples:
servo_motor: cleanups and changes"), that commit introduced further
bugs. This happened because the new pwm-servo alias that commit
switched to wasn't provided by any boards, so it wasn't built in CI.
Before that, however, the recommendation to use bbc_microbit in the
sample documentation was also buggy in a couple of ways:
1. bbc_microbit doesn't have the pwm-0 alias the sample
previously required, so it didn't build on that board
2. the documentation's comment to use pin 0 on the edge connector
is wrong; PWM channel 0 is wired to GPIO P0.0 on the SoC,
which is actually pin 21 on the connector
Fix it all up.
Tested on bbc_microbit. I verified the pinout and also made sure that
the sample correctly generates pulses from 700 to 2300 usec.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
The APIC timer is not supported e.g. with SMP (which will be enabled
by default soon as well) so the sensible choice is to default to HPET.
Also, the default makes more sense to be on the SoC side, so move it
there from the board defaults.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The boot time measurement can also run with the HPET timer so there's
no reason to restrict it to APIC.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Let the default value for SYS_CLOCK_HW_CYCLES_PER_SEC come from the
SoC instead. Furthermore, a default for HPET_TIMER didn't even make
sense since this timer doesn't do anything with the Kconfig value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Some kernel tests use `CONFIG_TICKLESS_KERNEL=n` with
`CONFIG_SYS_CLOCK_TICKS_PER_SEC=1` to detect when a test runs longer
than 1 second. These tests break if a tick is announced every time a
timeout occurs. Only announce if the measured duration since the last
tick is at least the duration of a tick.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Most boards run with 10 kHz ticks producing a period of 5 ms for 50
tick interval used in the timer periodic test. On Nordic 50 ticks
corresponds to 1.5 ms which is too short to complete the TC_PRINT()
call within the handler, causing the periodic timer to starve the
osDelay that would turn off the timer.
Adjust the period to be at least 5 ms or 50 ticks to avoid this
problem while not breaking other platform with slower tick rates.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Cortex-M has 24bit systick.
But this test by default set 1 TICK per seconds, which is
achievable only if frequency is below 0x00FFFFFF (around 16MHz).
20 Ticks per secondes allows a frequency up to 335544300Hz (335MHz)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
