As the nRF5x BLE controller uses TIMER1, TIMER2 and PPI
indices 0-13 (and 14-15, if PA/LNA feature is enabled),
the software based PWM driver needing 6 PPI channels has
to use PPI indices outside the BLE controller used range.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
- Renaming NET_L2_RAW_CHANNEL to NET_RAW_MODE
- Create a generic IEEE 802.15.4 raw mode for drivers
- Modify the IEEE 802.15.4 drivers so it passes the packet unmodified,
up to code using that mode to apply the necessary changes on the
received net_pkt according to their needs
- Modify wpanusb/wpan_serial relevantly
Fixes#5004
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Delete the native UART JTAG driver as we will be reusing
the Altera's HAL driver.
Add the shim driver support for Altera HAL's JTAG UART soft IP.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Delete the native timer soft IP driver as we will be reusing
the Altera's HAL drivers for most of the soft IP's.
Add shim driver support for Altera timer system clock soft IP.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Rename the Atmel SAM I2C driver based on TWIHS module to match the
convention:
<driver class>_<SoC family>_<hardware module used by the driver>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Various minor changes to the Atmel SAM (TWIHS) driver
- clean up variable names, comments
- refactor i2c_clk_set function
- do not save configuration in dev_data
- improve ISR NACK handling
- print "Device initialized" string
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Adds a new gpio driver for the NXP i.MX family of SoCs. Read, write,
configure, and callback API functions are all implemented.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Event ISR checks if the TX/RX interrupts is enabled instead
of the TXIS/RXNE interrupt status flags. Use the TXIS/RXNE
interrupt status flags to check which interrupt event
happened.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
STM32 I2C driver doesn't use the I2C API flags STOP/RESTART,
instead it uses its own RESTART flag. As a result, I2C API's
i2c_burst_write* funtions doesn't work. This patch makes
STM32 I2C driver to use I2C API flags.
Tested on: 96b_carbon, olimexino_stm32 (i2c_ll_stm32_v1)
Tested on: stm32f3_disco, disco_l475_iot1 (i2c_ll_stm32_v2)
Fixes: #4459
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
The interrupt priority on KW41Z is from 0..3. The value of 0x80 is
invalid, so lets set it to 0 for now as all the other interrupt
priorities default to 0 right now.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added conditionally enabled event state tracing support.
Needed for enhanced debug visibility of tight timed events where
normal print debug messages affect the timing of things. This is a
simple buffer that allows post analysis via gdb of what sequencer
events occurred.
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
- Removed some debug output and changed the level of others to reduce
the amount of information logged. The reason is that some of this is
causing false positive distractions.
- Removed enabling of FILTER error IRQ events. It isn't needed and is
only informational.
- Changed frame control AR bit inspection to use native retrieval
routine.
- Addressed some coding style issues.
Signed-off-by: David Leach <david.leach@nxp.com>
Changed the logic to reset the sequencer when a RX filter
failure has been detected. This also disables the RX timer
until the next watermark detection.
Signed-off-by: David Leach <david.leach@nxp.com>
- Reworked the driver logic around TX/RX to correctly handle the
expectations of the underlying 802.15.4 hardware IP.
- Fixed a problem with TX always reporting an error to the stack
which resulted in constant retries.
- Fixed bug in RX to TX transition which would occasionally cause the
driver to error the TX.
- Changed RX logic to ensure that invalid RX frames were not passed up
the stack.
- Simplified hardware timer usage to only use TMR3.
- Added RX watermark and TMR3 support to fix a hardware problem where
the hw IP can get stuck on a receive in noisy environments.
- Modified samples/net/echo_client and echo_server kw41z project config
files to provide enanced debug visibility into stacks and threads.
Signed-off-by: David Leach <david.leach@nxp.com>
Instead of passing net_pkt as is to the receiving side of the
interface, clone the sent packet and drop the sent one.
This is needed mainly in TCP where passing the same packet from
sending to receiving side is causing havoc.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
During large USB transfer it's pretty common to call ep_write whereas
the previous TX transfer is not achieved and so the TX FIFO space is
not available. Sleeping 20ms in this case introduce a relatively high
latency and reduce the throughput.
This can be observed when pinging the board with CDC-ECM net class.
ping reply is split into 2 USB TX transfer, the second one is only
triggered after 20ms, making ping latency > 20ms.
To fix this, just continuously read the FIFO availabilty and fire TX
as soon as possible.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
In the same way as dw driver, check that FIFO is empty before
writing any new data. This patch introduces a boolean semaphore
which is requested before any new TX transfer and released on
transfer completion.
This fixes usb-ecm support on 96b_carbon board.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.
By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.
When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.
Here are some outputs of the the command line
$ sudo ./tools/jailhouse cell stats tiny-demo
on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:
Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 7 0
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_xapic 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_msr 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:
- hello_world
- philosophers
- synchronization
The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.
Testing it is just a matter of:
$ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
$ sudo insmod <path to jailhouse.ko>
$ sudo jailhouse enable <path to configs/qemu-x86.cell>
$ sudo jailhouse cell create <path to configs/tiny-demo.cell>
$ sudo mount -t 9p -o trans/virtio host /mnt
$ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
$ sudo jailhouse cell start tiny-demo
$ sudo jailhouse cell destroy tiny-demo
$ sudo jailhouse disable
$ sudo rmmod jailhouse
For the hello_world demo case, one should then get QEMU's serial port
output similar to:
"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""
Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.
As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).
Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.
You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.
Other config differences from pristine QEMU defaults worth of mention
are:
- there is no HPET when running as Jailhouse guest. We use the LOAPIC
timer, instead
- there is no PIC_DISABLE, because there is no 8259A PIC when running
as a Jailhouse guest
- XIP makes no sense also when running as Jailhouse guest, and both
PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
config is set to
This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.
[1] https://github.com/siemens/jailhouse
Reference to Jailhouse's booting preamble code:
Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This will accomodate newer access models later, with variations of those
functions' contents.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
nrf SOCs are capable of waking from Low power state or
Deep Sleep state using sense configuration.
So adding support for this in nrf GPIO driver.
Jira: ZEP-2623
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
The Makefile was using the obj-$FOO = form instead of the ob-$FOO +=
form, so if both slip and loopback are enabled then only loopback will
get built.
Signed-off-by: Michael Hope <mlhx@google.com>
In order to be able to default Kconfig "Trigger mode" choice
in a board Kconfig.defconfig, this commit provides it with a name.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to be able to default Kconfig "Trigger mode" choice
in a board Kconfig.defconfig, this commit provides it with a name.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fixes#4429
Driver didn't work properly when a transfer consisted of multiple
messages.
Fix doesn't use auto end mode anymore. msg_done function waits for
transfer to complete and issues stop condition if necessary.
Tested with stm32f3_disco board and samples/drivers/i2c_fujitsu_fram
example adapted to use I2C_1 as I2C_DEV
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Fix TinyCrypt shim driver Kconfig dependencies.
Limit the scope of crypto_driver_api functions to driver file only.
Remove dead code from crypto_tc_shim_priv.h
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
GPIO_PIN_ENABLE, GPIO_PIN_DISABLE configuration constants overlap
functionality provided by pinmux driver. They usage makes the API
inconsistent. They are almost uniformly ignored by the existing device
drivers. Only few of them take these constants into account.
This commit deprecates usage of the two configuration constants.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Instead of every hardware number generator driver providing an
implementation of this function, use the random device API to
centralize the implementation of this function.
This is a very simplistic function that can be seen as a stepping stone
to refactor the random number generation in Zephyr.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This should clear up some of the confusion with random number
generators and drivers that obtain entropy from the hardware. Also,
many hardware number generators have limited bandwidth, so it's natural
for their output to be only used for seeding a random number generator.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Some "random" drivers are not drivers at all: they just implement the
function `sys_rand32_get()`. Move those to a random subsystem in
preparation for a reorganization.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Certain interrupt-driven APIs were excluded as they are intended
only to be called from ISRs, or involve registering a callback
which runs in interrupt context.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
spi_transceive_async() omitted as we don't support k_poll objects
in user mode (yet).
The checking for spi_transceive() is fairly complex as we have to
validate the config struct passed in along with device instances
contained within it.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Many APIs had two versions, by port and by pin, which called the same
API with different parameters. This has been reorganized to reduce
the number of system calls.
Callback registration API skipped.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
pinmux_pin_get() needs memory validated for the func parameter since
it's a pointer that gets written to.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The page_layout API returns pointers to kernel memory and is not
exposed to user mode. This is fine for flash_get_page_count()
and flash_get_page_info APIs since these copy the values, but some
redesign work will be needed to get flash_page_foreach() working in
user mode since we do not want the callback running in a privileged
state.
Due to the way that (even unimplemented) system call prototypes are
generated, the definition of struct flash_pages_info needed to be
moved outside of the #ifdef.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Straightforward conversion for adc_enable/disable.
adc_read() uses a sequence table, which points to an array
of struct adc_seq_entry, each element pointing
to memory buffers. Need to validate all of these as being readable
by the caller, and the buffers writable.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
i2c actually only has two entry points into the driver,
i2c_configure and i2c_transfer. All the other APIs are derived
from these.
All derived APIs now just call i2c_transfer() with appropriate args.
The handler for i2c_transfer() needs to examine the message array
and validate all the buffers involved depending on whether we are
reading or writing to them.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Waiting for tx to complete should timeout after 10ms
instead of blocking forever in case ack is not received.
Signed-off-by: Kamil Sroka <kamil.sroka@nordicsemi.no>
Adding sleep before TX FIFO flash fixes splitting networking packets
sent over USB endpoints making ECM broken since there is no flow
control other then frame sizes.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The situation when FIFO is not empty is not a bug and it is spamming
console when only bugs are enabled.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
The Designware FIFO is filled in units of 32 bit words, but the buffer
we are passed is not guaranteed to be a multiple of 4 bytes long, nor
aligned on a 4-byte boundary. So in theory we are reading 0-3 bytes
of unused garbage from the end of the array.
That's currently benign on supported platforms with this hardware,
which all support misaligned reads. But not all do. And the incoming
arrival of memory protection opens the possibility that those extra
bytes would cross a protection boundary and cause a crash or security
bug.
Do this right.
(Note that this is fixed to little endian byte order. The Designware
databook is frustratingly silent on the endianness it expects, but
existing hardware I can see is definitely LE and I see a few spots in
the Linux dwc2 driver that likewise assume LE).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The designware hardware in dedicated FIFO mode (which is all we
support right now for lack of shared-FIFO hardware) has one hardware
FIFO per IN (i.e. transmit) endpoint. But it doesn't assign them on
its own, it's the drivers responsibility to populate the TxFNum field
of the DIEPCTL registers with integer indices corresponding to the
desired FIFO.
We weren't doing that, which meant that all IN endpoints were sharing
the same FIFO zero which is supposed to be dedicated to EP0 control
transfers. The net effect is that sometimes outbound transfers would
be corrupted, showing data from the wrong endpoint. More often that
not this would leak from control transfers over to the
higher-bandwidth bulk endpoints of the application, but occasionally
you'd see a control transfer itself get borked and the USB device
would glitch.
Get this right and set the FIFOs properly.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is no particular reason this spot in usb_dw_tx() cannot be
reached by racing threads on the same endpoint, though existing API
usage in the tree is all unithreaded. The FIFO state read at the top
of the function must still be true at the bottom or else the packet
byte count will be corrupt.
Also, as described in an existing comment, the databook has some
scary-sounding warnings about access to the registers during FIFO
operations, even if they "should" be on separate endpoints and
unrelated.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Issue a error message, if the _mcr20a_read_reg fails.
Do not execute SPI burst read/write if the buffer is too small.
Unlock mutex if set_pan_id, set_short_addr or set_ieee_addr
fail.
Force abort of the sequence when the higher level changes the channel
even though a T or TR sequence is in progress.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
checkpatch returns the following errors:
"ERROR:COMPLEX_MACRO: Macros with complex values
should be enclosed in parentheses"
Let's fix all of them.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The WS2812 LED driver IC has a one-wire interface which encodes bit
values as pulse widths.
The ICs themselves are basically shift registers. Roughly speaking, a
"short" pulse shifts in a zero bit, a "long" pulse shifts in a one
bit, and an inter-pulse gap exceeding a reset time threshold causes a
pixel to latch the shifted-in color values. Each chip has an output
pin for daisy chaining. Refer to the chip datsheets and comments in
Kconfig.ws2812 for more details.
To meet timing without hogging the core, this driver generates pulses
using SPI. To work, this requires the MOSI line to stay low between
SPI frames, and for inter-frame delays to be less than the reset pulse
time.
There are other ways do it (PWM + DMA on some SoCs, GPIO bit-banging
if no other tasks need the core), but this is a reasonably
general-purpose implementation.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
LPD880x (e.g. LPD8803, LPD8806) devices are LED driver ICs which can
be controlled via a reduced SPI interface (clock and data only), and
support daisy chaining.
Add an led_strip driver for these devices.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This API covers drivers for strips, or strings, of individually
addressable LEDs. Both RGB and grayscale LED strip drivers can be
implemented within these APIs.
The API only provides for updating the entire strip, since not all
strips support updating individual LEDs without affecting the others.
Subsequent patches will add individual driver support.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This ensures DW_apb_i2c correctly transmits the slave address (7 or
10 bit) based on ic_10bitaddr_master when configured in master mode.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
The ic_tar and ic_sar were earlier set to 9 bits but now its
corrected to consider 10 bits.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
When the header file is located in the same directory as the source
file it is better to use a relative quote-include, e.g.
than a system include like
Avoiding the use of system includes in these cases is beneficial
because;
* The source code will be easier to build because there will be fewer
system include paths.
* It is easier for a user to determine where a quote-include header
file is located than where a system include is located.
* You are less likely to encounter aliasing issues if the list of
system include paths is minimized.
Authors:
Anas Nashif
Sebastian Bøe
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
No need to send FCS bytes as the monitor_15_4 is configured to not
expect them. If we change the monitor_15_4 to use them, then we would
need to put correct values into these two FCS bytes.
So cleanest solution is not to send FCS bytes at all.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
`rc` gets assigned values from function returning `int` and not
`u32_t`.
Fixes#4051.
Coverity-ID: 177219
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Loopback is a networking interface which doesn't actually transfer
any data via link layer externally, and instead just mirrors back
(i.e. any packet send to the loopback interface will be received from
it). This interface very useful for testing.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Make drivers/net/ be the place for misc networking-related drivers
(otherwise, we'd need to have a new dir per driver).
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Atmel SAM3X series has been recently converted to use ASF and
should now use common SAM family drivers. The i2c_atmel_sam3
I2C driver will be removed in the future.
This commit also changes the default I2C driver for Arduino Due
board from i2c_atmel_sam3 to i2c_sam_twi.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added I2C bus (TWI) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.
Tested on Arduino Due board.
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
STM32 UART driver was using a mix of LL/HAL APIs. This commit removes
calls to HAL API and replaces them with LL APIs. No functional change
have been seen during non regression testing.
But we could note a direct gain of 1Kb of ROM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32F0/3 I2C's independent clock source supports only
HSI and SYSCLK, not APB1. We force I2C clock source to SYSCLK.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Refactors the mcux lpsci shim driver to use the clock control interface
instead of calling CLOCK_GetFreq() directly. This will allow SoCs with
different clock architectures to reuse this driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the mcux lpuart shim driver to use the clock control interface
instead of calling CLOCK_GetFreq() directly. This will allow SoCs with
different clock architectures to reuse this driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use the clock control interface instead of calling CLOCK_GetFreq()
directly. This will allow SoCs with different clock architectures to
reuse this driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new clock control driver for Kinetis SoCs that have the system
integration (SIM) module. This will allow mcux shim drivers, such as
uart and i2c, to abstract the call to CLOCK_GetFreq() behind the
clock_control interface and thus be reused for SoCs with different clock
architectures.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
IRQ_CONNECT() was being expanded with the IRQ line for the first device
twice, causing spurious IRQs.
Should fix#4398.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This patch adds support for on board UART_0 on MSP-EXP432P401R-LAUNCHXL.
Driver makes use of driverlib available in ROM by default, thus saving
code space.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This is a USB controller driver for STM32F4xx devices using
the STM32 Cube HAL_PCD framework. This has been tested with
the cdc_acm driver on a 96b_carbon board (STM32F401RE).
This is a refactoring of:
usb: usb_dc_stm: Add support for STM32Cube HAL_PCD USB driver
Signed-off-by: Christer Weinigel <christer@weinigel.se>
[daniel.thompson@linaro.org: Removed STM32F40(157) defconfig changes
together with STM32F4Discovery pinmux and defconfig changes, updated
clock settings and pad configuration to match latest mainline]
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[giannis.damigos@gmail.com: Change uint*_t types to u*_t types,
change SYS_LOG_USB_DC_STM_LEVEL to SYS_LOG_USB_DRIVER_LEVEL and
update pinmux to match latest arm branch]
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Add pinmux configuration for USB OTG Full Speed.
Ports 11 and 12 use alternate function 10 for DM/DP.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Previously, there was boolean CONFIG_SLIP_DEBUG, which effectively
switched between "logging off" and "debug-level logging". Instead,
switch to CONFIG_SYS_LOG_SLIP_LEVEL (the naming of the option follows
existing conventions) which allows to select any of the standard 5
logging levels.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The current prescaler calculation incorrectly fails to configure the
desired frequency when it is possible to match it exactly. Fix this.
Without this patch, if the user requests frequency N Hz, and there is
a SPI prescaler that can match this frequency exactly, the actual
frequency chosen by spi_stm32_configure() will be N/2 Hz.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
There are 3 cases of possible allocation failures, only 1 of them
was logged. Now, all the cases are logged: 1) failure to allocate
net_pkt; 2) failure to allocate very first net_buf for it; 3)
failure to allocate additional net_buf for it (this latter was
the only one logged previously).
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
set_ieee_addr, set_short_addr and set_pan_id are now unused by L2, so
removing their exposure through the radio API.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Further support will need work per-driver basis, as soon as the L2 will
be able to make usage of such support.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Write-block-size values were filled for nRF5, STM32, QMSI, MCUX and
w25qxxdv devices.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
There are several issues with the dev_config union used as a
convenience when calling the i2c_configure api. One, the union is well
name spaced protected and doesn't convey use with just i2c. Second
there are assumptions of how the bits might get packed by the union
which can't be guaranteed. Since the API takes a u32_t lets change in
tree uses to using the macros to setup a u32_t and make the union as
deprecated.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If CS (Chip Select, known also as Slave Select...) is managed externaly
of the stm32_ll SPI controller, just config NSS line management
accordingly.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Supports both master and slave mode, standard and fast modes,
configurable timeouts, and a few other tunable settings.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Also provide their prototypes in `soc.h`. This should help
readability, since some ROM functions, with their names as provided by
Espressif, have sometimes the same prefix as Zephyr APIs.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Configuring an open drain driver is required by the I2C driver,
but the GPIO driver didn't support setting the drive strength.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
PINMUX_FUNC_A is set to 0, which coincides with the GPIO function in
many of the ESP32 pins. Use PIN_FUNC_GPIO by default inside the
GPIO driver, however, so the correct function is always selected.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
If the LF clock was already started, but wasn't initialized with
_k32src_start yet, allow it to run once. This is needed because if a
soft reset is triggered while watchdog is active, the LF clock will
already be running, but won't be configured yet (watchdog forces LF
clock to be running).
If the LF clock isn't configured with _k32src_start, the nRF5 RTC
won't count and the whole system will malfunction, as the kernel
depends on the clock source being working properly.
Signed-off-by: Thiago Silveira <thiago@exati.com.br>
This patch adds a routine which can be used to iterate over all flash
pages on the device.
This can be also done by using flash_get_page_info_by_idx(), but that
would add an unnecessary loop over the layout array for each page.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
802.15.4 is the networking hardware available in KW41Z SoC (and
supported by Zephyr). So, if networking in enabled, automatically
select the corresponding driver. This is similar to how frdm_k64f
automatically selects Ethernet driver, 96b_carbon selects BLE/IPSP
drivers, etc. (But we apply it on SoC level to reuse across the
boards.)
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Some our Zephyr tools don't like seeing UTF-8 characters, as reported in
issue #4131) so a quick scan and replace for UTF-8 characters in .rst,
.h, and Kconfig files using "file --mime-encoding" (excluding the /ext
folders) finds these files to tweak.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
