Enable icount mode for qemu_xtensa platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_a53 platform, The icount shift
value is selectd based on cpu clock frequency of this platform.
The virtual cpu will execute one instruction every 2^shift ns of
virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m3 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_cortex_m0 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Enable icount mode for qemu_x86 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
Remove the existing qemu icount configuration because icount mode
will be controlled by Kconfig QEMU_ICOUNT so that none suitable
cases(especially networking cases) can exclude icount configuration
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
The length field for the MCUBOOT slot partitions in Nordic platforms
has always had an extra leading zero suggesting it's a 40-bit value,
being stored in a 32-bit field. Remove the incorrect leading zero to
reduce misunderstanding of the field.
Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:
- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
for macros which are equivalent to
DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name
Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.
This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
When we build Zephyr as Secure image on nRF340 Application
MCU and nRF9160 SoC we would like to pass the information
about the reserved memory area allocated to the Non-Secure
images. The information may be needed to apply proper
security configuration. We add a "chosen" node in board .dts
file for this purpose.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_ns and sram0_bsd to represent physical
ram; these are just portions of sram reserved for the non-secure
image and the bsd library, respectively. Thus we can remove the
compatible property from these nodes. We also make use of
'reserved-memory' to represent the different memory partitions
to be used by the nrf9160 builds.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
sram0 node is needed to hold the size of the
total, physical SRAM available on nRF9160 SoC.
We use sram0_s to represent the Secure image
SRAM for nRF9160_dk builds.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We do not want sram0_shared to represent physical ram;
this is just a portion of sram reserved for shared memory
between Application and Network MCU. Therfore, we remove
the 'mmio' compatible property and transform this node to
a reserved-memory node definition, inside which we define
the sram0_shared node along with its reg property.
In addition we correct the documentation about the shared
memory, stressing that it is placed after the image RAM of
nrf5340 Application MCU (not after the secure SRAM).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
We should not be using sram0 for image SRAM in nrf5340pdk.
sram0 represents the physical SRAM and that one includes the
shared memory between the two M33 CPUs on the SoC. We should
not be re-sizing sram0 to account for the shared RAM; instead
we would like to have sram0 representing the whole available
SRAM.
For that, we define a new memory node, sram0_image to
represent the 'image' SRAM that is available for Zephyr
on the board. sram0_image is the chosen image SRAM for
default builds, i.e. when TrustZone is ignored
(TRUSTED_EXECUTION_SECURE is not defined).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move from a Kconfig to select/initialize the MAC address to using the
"local-mac-address" property in devicetree. If the property is set the
drivers will initialize the mac-address from the devicetree (unless the
mac address is all 0's). The MAC address might get overwritten by
either a driver specific means or by the setting of
"zephyr,random-mac-address" in the devicetree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Utilize the devicetree property "zephyr,random-mac-address" to determine
if a driver should use a random mac address and remove the associated
Kconfig options that enabled this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for TF-M to the MUSCA B1.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephy application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
This commit adds support for TF-M to the MPS2 AN521.
When the CONFIG_BUILD_WITH_TFM flag is set, a secure and
non-secure processing environment image pair will be
generated, with the Zephyr application image running on
the non-secure side.
The secure and non-secure binary images will be signed
for use with the BL2 secure bootloader.
An additional .hex file is also generated to enable
running QEMU with the AN521 binaries, `tfm_qemu.hex`,
which can be executed with the `-t run` option with
west, or `run` with ninja or make.
When configured for use with TF-M, the
`mps2_an521_nonsecure` board definition should be used.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
PSA level 1 requires secure boot. TF-M BL2 is the official
secure boot loader. It needs a BL2_HEADER_SIZE offset.
Align nonsecure address with TF-M's NS slot while TF-M BL2 enabled.
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Use DT_INST_SPI_DEV_HAS_CS_GPIOS() in drivers to determine if we should
utilize CS_GPIO base SPI chipselect handling. This allows us to remove
Kconfig option for this feature.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For HPET devices, configure it with fixed delivery mode because HPET
timer interrupt is needed to fuel the scheduler for all CPUS.
For all other type of devices, like UART, I2C, GPIO, Ethernet, etc.
configure them as lowest priority delivery mode, in which IO APIC
delivers the interrupt to the processor core that is executing at the
lowest priority among all the processors listed in the specified
destination. In this case, the device drivers can avoid the trouble of
handling repeated interrupts delivered to all CPUS.
Signed-off-by: Zide Chen <zide.chen@intel.com>
Swap this out and make the status a parameter.
Leave a couple of cases of DT_NODE_HAS_COMPAT().
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
These are redundantly checking a node's status twice.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Usually, we want to operate only on "available" device
nodes ("available" means "status is okay and a matching binding is
found"), but that's not true in all cases.
Sometimes we want to operate on special nodes without matching
bindings, such as those describing memory.
To handle the distinction, change various additional devicetree APIs
making it clear that they operate only on available device nodes,
adjusting gen_defines and devicetree.h implementation details
accordingly:
- emit macros for all existing nodes in gen_defines.py, regardless
of status or matching binding
- rename DT_NUM_INST to DT_NUM_INST_STATUS_OKAY
- rename DT_NODE_HAS_COMPAT to DT_NODE_HAS_COMPAT_STATUS_OKAY
- rename DT_INST_FOREACH to DT_INST_FOREACH_STATUS_OKAY
- rename DT_ANY_INST_ON_BUS to DT_ANY_INST_ON_BUS_STATUS_OKAY
- rewrite DT_HAS_NODE_STATUS_OKAY in terms of a new DT_NODE_HAS_STATUS
- resurrect DT_HAS_NODE in the form of DT_NODE_EXISTS
- remove DT_COMPAT_ON_BUS as a public API
- use the new default_prop_types edtlib parameter
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
With the new RI-2018.0 XCC, xt-gdb complains about not being able
to find register f0. Turns out that xt-gdb needs to be told which
file to look at (the file command) before a load command can be
issued. So swap these two commands in the load_elf.txt file.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit adds support for nRF52820 development on nRF52833DK.
Changes afffects:
- Introduce files related to board description.
- Add blank documentation file (for future update).
- configuration files for build process.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Changes:
- Added all required board files in /boards/arm/96b_aerocore2
- Modified pinmux for stm32f4
Most of the changes in this PR is based on reverse-engineering of the
PCB layout and following commits in the PX4 firmware repository for
the same board. The manufacturer does not provide and or generate
schematics and pinout tables for this board.
This PR includes almost all of the interfaces connected to the STM32
MCU, the only thing not included is the J9 and J8 headers that connect
to a 96Boards baseboard.
These headers are not vital to the functionality of the Aerocore2.
Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
The SAM V71 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The SAM E70 SoC configuration currently selects the `ARM_MPU` symbol
and this effectively forces MPU usage on the SoC.
This commit removes `ARM_MPU` selection from the SoC Kconfig since it
is intended to be selected by a board, and the `CPU_HAS_ARM_MPU` symbol
already indicates that the SoC supports ARM MPU.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Update dtsi and pinmux macros for stm32f7 family. Add sdmmc1 to dts file
for stm32f746g_disco. Also add board specific configuration file for
fat_fs sample.
Signed-off-by: Helge Juul <helge@fastmail.com>
Update the dtsi for stm32l471 (which the higher SoCs are based on) to
support the stm32-sdmmc disk access device. Enable the device for the
stm32l496g_disco board, and update the pinmuxing.
Note that the stm32l496g_disco board also has a card detect gpio
(MFX_GPIO8), but this is not supported yet. When not specified the
driver will assume a card is present.
Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com>
Use MSI as PLL source. This enables to run system clock at 110MHz.
To achieve this, voltage regulator should be set to scale 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Map lpcxpresso55xxx type boards entropy device to rng peripheral.
Apllies to all versions of lpcxpress55s69 and lpcxpresso55s16.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Given that the Minnowboard has relatively large memory, the default
number of pages allocated for page tables are not enough, and
resulting in asserting in the page table initialization code.
So change the number of pages to a large number to accomodate
various applications.
Fixes#24353
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Convert i2s_sam_ssc driver to utilize devicetree. We replace Kconfig
options for specifying the DMA configuration (channel, DMA device name)
with getting that from devicetree. We also get pincfg from devicetree,
however we still have Kconfig sybmols to specify if the RF or RK pin is
enabled.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Gen3 (formerly "mesh") Particle product line has a header that is
structurally related to the Adafruit Feather, and is generally
compatible with Featherwing shields. Provide nexus maps for both the
native header layout, and for the subset feather header layout, and
add alias labels for the peripherals that would be referenced from
shield overlays.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The LoRa shell and samples need a way to find the default LoRa
radio. Add the DT alias 'lora0' for the default radio.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
Refactors the fat_fs sample yaml to depend on a feature rather than
whitelisting specific boards. This implicitly extends the sample to
mimxrt10{60,64}_evk boards, since they already support the feature.
The only whitelist board remaining is the nrf52840_blip, which requires
a device tree overlay for this sample.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enables sdhc on the mimxrt1064_evk board. Configures pinmuxes and device
tree, and updates board documentation accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enables sdhc on the mimxrt1060_evk board. Configures pinmuxes and device
tree, and updates board documentation accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As we phase out per instance Kconfig symbols convert to utilize
DT_DRV_INST to initialize CAN instances.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clean up as we wish to move away from using these Kconfig settings.
Also removing them from the boards' default config.
Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
ARC_MPU_VER 2 has a strong requirement in
* size, must be >= 2048 bytes and power of 2
* start address must be aligned to size
It may bring a big waste of memory.
On the other hand, GEN_PRIV_STACK is used for ARC_MPU_VER 2,
it conflicts with MPU_STACK_GUARD.
So considering the limmitations, remove MPU_STACK_GUARD for
ARC_MPU_VER 2
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Fix node status to "okay" instead of "ok" which doesn't
seem to be in used anymore across the tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Once the TPM driver and the required configs have been added,
now this patch enables the usage of the PWM framework on KW41Z
SoCs. As such, the DTS gets the proper nodes and the pinmuxing
is done according to the configuration requested.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Allow to flash either Cortex M4 or M7 with OpenOCD
(depending on which Board/Core has been compiled)
Command: west flash
Warning: Dependency with recent OpenOCD patch:
Windows: https://gnutoolchains.com/arm-eabi/openocd/
version 20200408
Linux : http://openocd.zylin.com/
SHA1: 0a804222da63c5f849efa23b019a59e2dea76842
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
The Kconfig I2C_[0-9] sybmols don't have any meaning for the majority of
SoCs. The drivers doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
* Define USB driver for base stm32wb device.
* Enable USB for the nucleo_wb55rg board.
* Properly initialize USB power + clock for the platform.
Signed-off-by: Pete Johanson <peter@peterjohanson.com>
x-nucleo-iks02a1 shield is an arduino compatible companion board
which can be used on top of Nucleo standard boards for industrial
applications. It extends the Nucleo functionalities adding following
MEMS sensor support:
- ISM330DHCX 3-axis accelerometer and 3-axis gyroscope
- IIS2MDC 3-axis magnetometer
- IIS2DLPC 3-axis accelerometer
- IMP34DT05 digital microphone.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Enable I2S_STM32 in the soc common part, so it will no
longer be required in board default configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Rename a few cases of DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY that snuck
in after the initial global change.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear. As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the asynchronous UART API testing support on the SAM
E54 Xplained Pro board.
The SERCOM1 module is used as the secondary loop-back UART, which is
required to run this test.
Note that no external UART loop-back connection is necessary to run
this test, because the SERCOM1 UART TX and RX pads are configured to be
internally connected; it is, however, still necessary to configure the
pinmux because the module pads are not connected until the pinmux is
configured.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Following other drivers, Kconfig based instances are now entirely
removed. In order to do this change, PWM nodes in board DT files have
been given a pwm{N} label so that both:
- DT API checks such as #if DT_HAS_NODE(DT_NODELABEL(pwmN)) can be
used (N being PWM instance number).
- DT references can be written as pwms = <&pwmN x y>; instead of
pwms = <&{/soc/timers@XXXXXXXX/pwm} x y>;
This approach is also used on the Linux Kernel.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
For auto doc generation purpose, get name value of boards' yaml files
in sync with name provided as board name in .rst file
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The Kconfig PWM_[0-3] sybmols don't have any meaning for kinetis family
SoCs. The driver doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Kconfig PWM_[0-3] sybmols don't have any meaning for nrf family of
SoCs. The driver doesn't utilize them and no sample or test code does
either so we can remove setting them in board Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the `i2c-0` alias for the Atmel SAM R21 Xplained Pro
board, as required by the I2C test.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
