- Sample application now pulls data continuously.
- Adds information on the arduino analog input pins and ADC channels.
- CHANNEL is defined as a macro.
- BUFFER_SIZE is defined as a macro.
- Sets the sample to run on repetitive mode on ARC architectures
(applies to Arduino 101 ADC).
Change-Id: I6201fea3a98b5394c05eb3ac570793629431ac02
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
After exiting a deep power down mode a dummy conversion is required.
Change-Id: I98dad19e168984efe7af6ad360d0cc46e6603736
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Curie specs states that the ADC_PWR_MODE_STS bit in the
IO_CREG_SLV0_OBSR register must be polled to check if
the requested power mode equals the current power mode.
The bit is set to 1 when requested and current modes match
and the bit is located as the bit 0.
Change-Id: I030d7693d36fb96f09a9cbdd404118674fcb089a
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
ADC DW IP requires a calibration process each time the
IP recovers from a deep power down mode.
Change-Id: I2e02d1987af9addd9cb08a4e4e8d3848ad5b623c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
This patch removes the checks related to CONFIG_CC_STACKPROTECTOR_
REGULAR and CONFIG_CC_STACKPROTECTOR_STRONG options since these
options don't exist in Zephyr. According to 186ab6552, they were
copied from Linux but further clean up was missing.
Change-Id: I1d8b4f47319a54b68b6f0b5aec1feb0a247e72e9
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.
If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used
Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On NANOKERNEL level only of course. Some devices, initialized at this
level, may require to get the clock running already.
Change-Id: Id2dd830d915474aac6c080068c2cf356cf841e0c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Controller should not be enabled while configuring or setting up a
transfer call. It's enabled once the transfer call is ready to proceed,
and disabled once the last interrupt has be raised.
Change-Id: Ib9125a3600971b57e642730682f2b3bfb91b1e02
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On Quark SE, SPI might require GPIO to be ready before hand, to emulate
CS, thus providing an option to tweak the intialization priority for SPI
DW driver.
Change-Id: Ifa373948ac8227bf6e4ed1113bcb4dc9139b6663
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
It might be necessary to emulate CS through a GPIO pin depending on
these 2 conditions:
- the controller's CS pin is not wired, and thus a GPIO pin is the only
option
- The controller is unstable at a certain frequency and cannot set/unset
CS reliably. This is actually a possible issue on DesignWare's SPI
controller in Quark SE or Quarks D2000 where it has been found
unstable at 1Mhz and above.
Change-Id: Ib6a06577906c005ddd347070d476a367a9c3da8a
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
- Refine how DFS is calulated now that it is strictely used to
manipulate buffer lengths.
- Fix threshold limit
- Tune RX threshold relevantly (reduce it if rx_len is lower than actual)
- Don't push more than available left space in FIFO
- Tune the private structure to lower memory space occupation
Change-Id: I65b1b48b996b2104cebcb24cc366fb4dcbf7d53b
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
IMR and ISR bits are same, but it stil better to differentiate them
properly. Also fixing naming where all ISR ends with an 'S'.
Change-Id: I2fc1e1d8d2743c3d98f5da40a5f4720a85c4f9a7
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
On ARC, the SPI IP block might be accessible only via user extended
auxiliary registers, which requires different instructions to read from
and write to.
Change-Id: I3aa5f223938a9aed7795de4aedc64bd529d62942
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Registers offsets are hopefully all the same, but size differs.
On x86, thus 32bits support, CTRL0 or DR for instance are 32 bits r/w.
And DFS on 32 bits support is placed differently as well.
Change-Id: I5115d5c3c9bba71ece4a6f4a1d3d2fdc203c8da1
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Only 8 bit frames were supported. Added support for bigger data frames
which can go up to 32 bits (on 32bits version of the controller, 16 bits
otherwise). Store the frame size in bytes during configure, and use it
during pull/push to read/write correct frame size.
Change-Id: Iae8c55442e0a205403aa3febd1811b36aaf4c5b6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
If SPI_INTEL is not requested, no need to instanciate specific value.
Change-Id: I5f41d919e258e420f2bd099db88ed2259f9cd27e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Reported by Ramesh Thomas, the loop mode is included in the mode
configuration and not as a standalone bit. Also rewording word_size
parameter documentation.
Change-Id: I1e3337087316f56d58e843278b9c65e9f4f5476f
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quark SE SS provides 2 valid GPIO controllers, thus enabling the built
test case for it.
Change-Id: I46c6ceb3d4fe78a87c095e24851d289720524a9c
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Enable both controllers by default if GPIO is enabled, providing all the
necessary information.
Change-Id: I5aab00324b10492eefb67e9595da491775cbd95d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
There is no such thing as "IA" in Quark SE SS as it is an ARC core. Plus
for this very specific feature it does not require the ARC aux regs
instruction to read/write in the given mask address.
And fixing also the CONFIG_ option to check.
Change-Id: I1f63348ec85f6e006795f7641c912a30fc003709
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Quarks SE owns a GPIO controller which is always on (so not clock-gated)
thus providing it base address, the pins it handles etc...
Change-Id: Ifceb7cb74e763a91130d615ba19756ddcbe97a23
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This is valid only for Quark SE and Quark SE SS, where it requires to
unmask the interrupt for each specific controller. Thus making the
function generic, using the parameter as the specific mask base address.
Change-Id: Iea0a412b8d94a1ab5e1f3e339eaf632eacee5797
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a sample app to interface with TI INA219 power monitor.
The values used in the app are for use on Adafruit's breakout board
(https://www.adafruit.com/products/904).
This assumes the slave address is 0x40, where A0 and A1 are all
tied to ground.
Change-Id: I4116629171a98be6f2b9aa422dd3eb386b4d59c2
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The original value of 128 was selected more or less randomly, and
isn't sufficiently large enough for QA needs.
Change-Id: I8a9fcc86d6b5fa7dc5ba05896c62f7dd608f9ed2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Updating the SDK version to 0.7.1 and the download link for it.
Change-Id: I63c4d57fdc96f60426af8610c7f9ac69e79fe69c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This adds very basic support for running on Arduino Due.
Only the nanokernel hello_world has been tested.
Change-Id: I42b83d7f23ff88f709d2d6f2d43c6d29c82b9d32
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds driver for the UART controller on Atmel SAM3X8E.
This UART controller only has two wires for RX and TX, and
does not have flow control (e.g. CTS, RTS) or FIFO.
Currently, the driver does not support any interrupt driven
operations.
Change-Id: I63720bccfb70a89888353b8ee3dfc4b80793dc01
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds initial support for Atmel SAM3X8E processor, which is
based on ARM Cortex-M3. The SAM3X8E is being used on Arduino Due.
Change-Id: I199efcf29629f9ebacad474e5edc91bc3757f613
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This removes the default flash and SRAM base addresses from the ARM core
Kconfig file. Each individual SoC/processors Kconfig has to define them.
This is in preparation to support Atmel SAM3 family processors as they
have different base addresses.
Change-Id: I97ea9b43386d1e286ee692f583c97cfbb5399b0f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Introduced by commit 01d6f9f5ee0867f6ee8dc1506c2ebe62d9f296bb
Reported by Gustavo Lima Chaves
Change-Id: Ic29c33f4339c83a55ca45e93000cbc07b8dadbd2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Introduced by commit a6873a00d816daf303b0380dda91accd28df6497
Reordering the irq config function, and removing useless parameter.
Change-Id: I2d22cfe81153b104044d8672dd57115138437ed9
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
When ARCH is specificed on the command line the parsing process
is messed up and non-x86 platforms fail.
Change-Id: If63f243bce3cd305ce291de83bbd90c15b4c861e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is needed for setting up an image that runs entirely from SRAM,
including its vector table. Ensure integrity of relocated vector table
by using serialization instructions when moving the vector table to
ensure it has been fully written before something makes use of it.
Change-Id: I00c600d557c87c75847f67fbc42f1c2c16157608
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This reverts commit 778d5b11c5327be4b40c7745e9beaecfd6327e13.
This patch has been identified as breaking the build when trying
to manually build non-x86 applications.
Change-Id: I1857745049dfef7193de58737108314b7aae01c5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This option misunderstands how XIP works. The IDT is ALWAYS in ROM,
the question is whether crt0 will copy it into RAM or not. You can't
save ROM space in this way.
Change-Id: I58025e3d71ead35730d0a5026213299b4fcb5eb9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is being removed for a few reasons:
- AFAICT this is the only API in Zephyr that follows an allocate/free
model.
- There are no public APIs in the interrupt subsystem for releasing
or reconfiguring an interrupt. This code was relying on arch-specific
private APIs. If we really want to keep this capability we should
make these APIs public and consistent across arches.
- The use-case for this API is not clear, as Zephyr is not intended
for hot-pluggable peripherals. Built-in hardware tends to need its
interrupt for its entire life cycle.
- The current implementation of dynamic interrupts on x86 does not
support freeing a dynamic IRQ that was reserved with
irq_connect_dynamic(), causing this code not to work. To add this
would require reimplementing _get_dynamic_stub() to use a bitfield
or set of bitfields to track unused stubs rather than the simple
counter it uses now.
Change-Id: I7a03c134fb3498b91a1816318a88b293e26b846c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are not (yet) used anywhere and generate unnecessary warnings.
Just remove them.
Change-Id: Ibae472c4a639466c221cdc354232780db04e963e
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
This patch introduces the QMSI I2C driver which is simply a shim driver
based on I2C driver provided by QMSI BSP.
This initial version supports only I2C_0 controller in 'master' mode.
Due to some issues with qm_i2c_master_irq_transfer API, the driver uses
the polling APIs from QMSI. This means that the current thread doesn't
sleep (i.e. is not scheduled out) while the I2C transfer is carried out.
The qm_i2c_master_irq_transfer() issue is under investigation.
Below follows the missing features which will be addressed by a new
version of this patch or by upcoming patches.
* Block the current thread until the I2C operation has actually
completed.
* Add support for multiple controllers.
* Add support for slave mode.
* Add support for suspend() and resume() APIs.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_I2C=y
CONFIG_I2C_QMSI=y
Finally, due to the lack of proper support for Quark SE in QMSI 1.0.0,
this driver requires QMSI version greater than 1.0.0.
This driver has been tested only with Quark SE based boards.
Change-Id: I369992c7b5fe37f7e0b45be7f19e667ad1fca9ac
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
NBLE defaults (eg for BLUETOOTH_MAX_PAIRED) were not limited to
!BLUETOOTH and resulted in overwriting BLUETOOTH defaults.
Change-Id: I1e4a90c00c15252bb3db927b42641f9a479f4aa6
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
Select cannot be used for int type of variable. This will stil work
correctly as default value is provided. Fix following:
drivers/nble/Kconfig:50:warning: 'BLUETOOTH_MAX_PAIRED' has wrong type.
'select' only accept arguments of boolean and tristate type
Change-Id: I15951a3ba9efa11e1c18a1e90eb708ced08ad357
Signed-off-by: Szymon Janc <ext.szymon.janc@tieto.com>
This converts the i2c_quark_se_ss to use the static IRQ API.
Note that, even with separate config functions for each instance of
the driver, it is still saving both RAM and ROM space.
Change-Id: Ieb555ff281b384d87d8e69f6914878bbee0e2ee9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
An application will not care about the implementation and will want
to only reference a well define name for the IP, the configuration
system will take care of the rest.
And application will bing to the drivers this way for example:
dev = device_get_binding("WATCHDOG");
Change-Id: I8a0fde34602320de643a0ad911d19c9985600e7e
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
nble sample is a copy of peripheral sample which now has support for
testing nble driver so a dedicated application just for that is no
longer needed.
Change-Id: Ia8ea2262fc2472a54c81b90eb86d9c0d4b12f42d
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
