This commit provides dts file for nucleo boards.
For now dtsi files only populates uart nodes so other nodes
are not taken into account into board dts files.
Change-Id: Ide95a8ba3671b91ff0311b7671e77b3bf96db297
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit provides dtsi files for available stm32 base boards.
For now only uart nodes and IRQ number are provided in order to
enable delivery of coherent material.
It also clears additional content from stm32f103xb.dtsi
Change-Id: I62d932c7f22b56e95bcd9566ce39e14a393dd640
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As there can be a large number of FLASH & SRAM sizes for the same SoC
having a dts/dtsi for each one would be extremely painful. Lets just
use some #defines to set that FLASH & SRAM sizes based on the SoC that
is being built.
Change-Id: I06388ada4e49ed3d576da31150288512bb6b4485
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
I2C_SHARED_IRQ, I2C_0_IRQ_SHARED, I2C_0_IRQ_DIRECT Kconfig options
are DW driver specific. Its presence is confusing for a user of any
other I2C driver than DW. This patch renames these options to include
DW string and makes it visible only for DW I2C driver. This is a
similar implementation to that used by ETH DW Ethernet driver.
Change-Id: I795506f9b103c028a22317df9ad632dce5cd1343
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
By default a factory new SAM E70 chip will boot SAM-BA boot loader located in
the ROM, not the flashed image. This is determined by the value of GPNVM1
(General-Purpose NVM bit 1). Updated flash procedure will ensure that GPNVM1
is set to 1 changing the default behavior to boot from Flash.
Change-Id: Ic6334c9d4743a7665fc944e8f49fc1467ecda40d
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This patch modifies the DTS file to make the inclusion of the
bluetooth UART port conditional on CONFIG_BLUETOOTH option.
Issue: ZEP-1745
Change-Id: Iea8dc60fe17d131d8e3765e1962b25d157065c67
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add support for nRF5x series GPIOTE based PWM driver
implementation.
Provides upto 3 pins/channels using one HF timer, two PPI
channels per pin, and one GPIOTE config per pin.
Change-id: I6056b199ec2cff595ba8fea9f659a0338ed4635b
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
sys_slist_merge_slist shall reinit the appended list not the original.
Change-Id: Iacd5244d0243b7ebdb110991574e9e1d265ced14
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Correct the way interrupts are enabled and disabled using the INTENSET
and INTENCLR registers, which ignore all 0s written to them and are both
positive registers.
Change-Id: I052548b0255d9d5ae36b2a708ed1968ae3ab1d06
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add openocd.cfg to control flashing and debugging of the
olimexino-stm32 board
Change-Id: Ia40d964b737792864efd85076bc599b2de15ebb0
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The CONFIG_FLASH_LOAD_OFFSET allows the zephyr image to be placed at
an offset from the start of flash. This is useful for situations,
such as with a bootloader, to allow the image to not occupy the very
beginning of flash.
Complement this by adding a CONFIG_FLASH_LOAD_SIZE config, that can
constrain the size of the flash image. With the default of zero, the
behavior is as before, with the image allowed to occupy the rest of
the flash. It can also be defined to a non-zero value which will
constrain the image to occupy that many bytes of flash.
Although this is defined generally, it is currently only supported on
cortex-m targets.
Change-Id: I6e4a0e79c8459f931cd4757c932d20dac740f5f6
Signed-off-by: David Brown <david.brown@linaro.org>
Instead of FLASH_LOAD_OFFSET being something specific to cortex-m, add
it generally to misc/Kconfig, along with a hidden config
HAS_LOAD_OFFSET which can be selected by the architectures as they add
support for the functionality.
Change-Id: I256ff8cf4e9b8493b26354c3b93fe1f7017d4887
Signed-off-by: David Brown <david.brown@linaro.org>
The schematics of the BBC micro:bit are hard to find, and its official
web-site doesn't document the mapping of the edge connector pins
numbers the nRF51 GPIO pin numbers. Provide helpful defines for this
in the board.h file.
Change-Id: I52ce1d61558703b6aa5a5d073ccd222f27fa8760
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
ztest has a number of assert style macros and used a baseline assert()
that varies from the system definition of assert() so lets rename
everything as zassert to be clear.
Change-Id: I7f176b3bae94d1045054d665be8b5bda947e5bb0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
gcc only understands -mlongcalls form of this option, xcc understands
both. Use -mlongcalls for building with both xcc and gcc.
Change-Id: I93f65ccbc97429ae564f1986120b37ce205ee38c
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
__BYTE_ORDER__, __ORDER_BIG_ENDIAN__ and __ORDER_LITTLE_ENDIAN__ are not
defined when building with xcc, but are defined when building with gcc.
Define them conditionally.
Change-Id: Ib205ffee28360aa240d61731b7a3d6f45401b4c1
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
simcall must be in the volatile asm so that gcc does not optimize it
out. It also needs "memory" clobber to make sure data passed through
memory buffer is actually written back before the simcall.
Change-Id: I410b7348bf605d0d08f81ec5395f6cb144f33a43
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The directive exists for platforms that require more stack space than
usual. However, it wasn't being applied to the ztest thread stack
which ztest-enabled cases are run on.
Fixes numerous failures on xtensa simulator targets.
Change-Id: Iafa84de002421f03729c0f0cdeefdea51842ae32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A recent patch added some new tests here. Unfortunately,
the current stack size value of 512 was too small for Xtensa.
Increase it to 1024.
Change-Id: I16c52b74412cbd7665e774ce3baed260885ddb9b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A recent patch pinned the stack size for this test at 1024
instead of the platform default. This value wasn't sufficient
on Xtensa. Set to 2048, which was the default on most platforms.
Change-Id: I9a9d5fd448d2377aaf782c2c093a16147f31886a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The issue was that cpStack was changed to a memory buffer by commit
https://gerrit.zephyrproject.org/r/#/c/12816
However the assembly code was expecting it to be a pointer and thus
issuing an indirection, that leads to wrong addresses.
The fix removed this unnecessary indirection and thus the inherent
invalid memory access exception.
Issue: ZEP-1997
Change-Id: I843f049212f2d116a01b05367a284209f463a5e7
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
The core build in the SDK does not have a timer, making it impossible
to use this core with most of the sanity checks. We are working on
getting a special package of cores for Zephyr which meet our build
requirments; until then, remove this core as it doesn't build.
Change-Id: I3fa201f3c6b5724501e8cb1e1b8ba631436ebc23
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Yes, revert the revert, was a little too quick to apply this. The fix
is to cleanup the dtsi file in question.
This reverts commit 6702686976.
Change-Id: I933fad9d96ec6375eda33f0b012349f1c39e261f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In general we should be using hardcoded addresses in the dtsi files
rather than getting ifdef from other places. As the unit address of the
node is typically based on the address in hex w/o the '0x' we can't just
use #defines directly.
Change-Id: I0e17e001151728d16842806d9407e66e6e5129cf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
* CONFIG_SOC is now properly set and we do not need a separate
XTENSA_CORE build variable
* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed
* There is no default SOC selection, it is now done explicitly in
the board's defconfig
* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
uppercase> to conform to established style.
Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Use UNALIGNED_GET and UNALIGNED_PUT throughout the networking stack to
access fields from the IP address structure. These structures can be
mapped directly to buffers and the macros are required for correct
unaligned memory access.
Jira: ZEP-2012
Change-Id: I55f9da7b143a22fa869d5d215c661de988cd9b91
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
net_nbuf_append_le32 helper appends le32 data to the packet, this is
needed in some Thread headers using LE data.
Change-Id: I04233ca064c2e23ec5c53979ac234adfe0ccb9dd
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This can be useful to override the default value, for testing.
Change-Id: I23b559152c71955ff5aa6fd3643f1f40f5594194
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This permits to tweak the TX power in dbm.
Change-Id: Idadff397941a39010ce3c374d9ca74b777934626
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This way, the driver will be able to pass the RSSI of the frame it just
received.
Change-Id: I08e7565e35b4fb087cf348bce01722ab25d59f0f
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This does not save any space but sets the fields in the
structs in more natural order. Move IPv6 related
fields in net_if into internal ipv6 struct so that all
IPv6 fields are located inside one struct. Same thing
is done for IPv4 fields which are now located inside
IPv4 internal struct in net_if.
There is no functionality changes by this commit.
Change-Id: I7d72ec0a28e2b88c79a4c294655d5ef6da6ccb25
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Shuffle the fields to different order in net_if_addr struct.
This saves space in net_if struct. This saved 4.8% memory,
640 bytes in original versus 608 bytes after this commit, when
allocating net_if using minimal amount of address counts and
IPv4, DHCPv4 and IPv6 enabled.
Change-Id: I591543cded587178cf6f82189953bb2e99c2188a
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
So manipulating it requires to be ready to swap it if the CPU is BE.
Change-Id: I8d657c31cecfc9f3fcd010efbb6d090bf021f5f5
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
DNS resolving is better done with DNS resolve API so remove
the DNS client API which is quite hard to use.
Change-Id: Ide4973a5be674414ea6e04a35c938195cce40b6a
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Modify the code to use DNS resolve API instead of DNS client API
as the latter is being phased out.
Change-Id: I6a7618d770621fee1f502d2bc277a162c589108a
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
We need a way to know when IPv6 address is successfully set
into network interface.
If IPv6 DAD (Duplicate Address Detection) succeeds or fails,
we send a management event for that. This can be used by
other components to detect when the network interface is in
usable state.
Change-Id: Ifb22415fe21f31f5dba4f55455d6e0f89b414d32
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Some of the IPv6 utility functions were missing const in
one of the parameters that are not modified by the corresponding
function.
Change-Id: Ic9fe53daac288570c14423fd9410dcf15d1c5cfa
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
