In the POSIX architecture, with the inf_clock "SOC", time does
not pass while the CPU is running. Tests that require time to pass
while busy waiting should call k_busy_wait() or in some other way
set the CPU to idle. This test was setting the CPU to idle while
waiting for the next time slice. This is ok if the system tick
(timer) is active and awaking the CPU every system tick period.
But when configured in tickless mode that is not the case, and the
CPU was set to sleep for an indefinite amount of time.
This commit fixes it by using k_busy_wait(a few microseconds) inside
that busy wait loop instead.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
In the POSIX architecture, with the inf_clock "SOC", time does
not pass while the CPU is running. Tests that require time to pass
while busy waiting should call k_busy_wait() or in some other way
set the CPU to idle. This test was setting the CPU to idle while
waiting for the next time slice. This is ok if the system tick
(timer) is active and awaking the CPU every system tick period.
But when configured in tickless mode that is not the case, and the
CPU was set to sleep for an indefinite amount of time.
This commit fixes it by using k_busy_wait(a few microseconds) inside
that busy wait loop instead.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
If shell UART backend was enabled and logger uart backend was
not explicitly disabled then both were used resulting in logs
being printed twice on terminal.
Patch modifies default state of log uart backend to depend on
state of shell uart backend.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Now that Cortex-M7 cache issues have been fixed in commits 828ae6b8 and
13972693, it is possible to safely enable the MPU on the STM32F7 SoC
series.
Note that the ITCM area is not mapped into an MPU region. This should
not be an issue for now, as Zephyr does not provide yet a way to
populate and use this area.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Previously we had a set of magic #define's in board.h that would both
enable and set the GPIO controller & pin if a given board used a GPIO
for USB VBUS. Now we make it a proper Kconfig set of options that
specify if the feature is needed, the GPIO controller device name, and
pin number. In the future this should move to devicetree.
Updated the related boards that used this feature to set the Kconfig
options in the Kconfig.defconfig
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Specific code is present GPIO_DEVICE_INIT_STM32 in
GPIO_DEVICE_INIT_STM32 to handle LL_APB2_GRP1_PERIPH_AFIO bit.
Though, this bit is already included in device tree information,
in clocks property, 'bits' field, which carries for each GPIO,
both LL_APB2_GRP1_PERIPH_GPIOX and LL_APB2_GRP1_PERIPH_AFIO.
Hence, it is already taken into account in
CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS and it is redundant
to handle it in GPIO_DEVICE_INIT_STM32 macro.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added support for ST B-L072Z-LRWAN1 board configuration.
This board uses the same MCU as Dragino-LSN50.
Signed-off-by: Aleksandr Makarov <seems.deviant@gmail.com>
Removed pin 20 which by default is connected to QSPI memory.
Removed conflict with default pin assignment for UART 1.
Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
Add a shell that implements "promisc [on | off] <interface>"
command to toggle promiscuous mode support.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Pass the promiscuous mode OFF event properly to device driver
instead of just toggling the network interface flag.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Patch introduces sensor model to mesh badge application. Along with
model definition a sensor get message is implemented and handled on
server.
Signed-off-by: Grzegorz Kolodziejczyk <grzegorz.kolodziejczyk@codecoup.pl>
This patch introduces new screen to mesh_badge application. Sensor
screen shows measurements from board sensors updated every 2 seconds.
Signed-off-by: Grzegorz Kolodziejczyk <grzegorz.kolodziejczyk@codecoup.pl>
MSYS support was added as a stop-gap while native windows support was
unsupported. Now that Native windows support is stable we can drop
support for MSYS.
Dropping support for MSYS fixes#11260 and allows us to spend more
resources on native windows support.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Convert the BMI160 to use Device Tree to get SPI and GPIO params instead
of Kconfig. Updated samples, tests, and arduino_101_sss board support
for this.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add #pwm-cells to the sifive PWM binding and dts files. This is to
support have a pwms clients work properly.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The error check was wrong, if we could send the packet then
we free it. If sending fails, then let the caller to decide
what to do with the packet.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Flush the promiscuous queue after all the clients have turned
off promiscuous mode. This makes sure that we do not leave any
RX packets hanging on the queue and waste memory.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Zephyr isn't ready to handle interrupts yet, until the
threading/scheduler are set up and we make our first context switch.
This was a semi-hidden bug: only the timer interrupt would actually
get unmasked before the system was ready, and obviously would never
have time to fire a tick before the system completed initialization.
But a combination of system load and a new version of Qemu (which
seems to be more sensitive to non-deterministic timing glitchery) has
made this visible. About 2-3% of the time when run under a full
sanitycheck, the qemu process will get swapped away for long enough
that the tick timer expires before _Cstart() has reached
enable_multithreading().
It looks like the original code was cut and pasted from another
implementation, which was expected to call into an "application"
main() routine that wanted interrupts ready.
Fixes#11182
(Note also that this code is not used for ESP-32, which has its own
startup path)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Application should be responsible for enabling various drivers and
features, we should not enable everything by default.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add "Multicast Promiscuous Enabled" (RCTL_MPE) bit definition and
use it for the receive control register (RCTL) initialization.
Multicast needs to be enabled in order for IPv6 auto-configuration
to succeed.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
The initial sequence was wrong and led to the missing interrupt
problem with netdev backends where the incoming traffic
appears immediately (tap).
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
If ARP header contains invalid fields then drop the packet.
Fixes#11257Fixes#11254Fixes#11253Fixes#11248
Signed-off-by: Ravi kumar Veeramally <ravikumar.veeramally@linux.intel.com>
STM32F103 micros starting from 64-pin (xE) packages upward have
available port G. This patch defines a dts binding for them.
Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
Update olimexino_stm32 configuration to match with default
configuration guidelines:
- Configure available UEXT connector which is available
on olimex boards.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Provide CONFIG macros for clocks bits and bus properties in fixup
files and use them to simplify logic in uart devices instanciation
code
Fixes#10448
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The ARMv8-M Memory Protection Unit document indicates that a DMB
instruction must be used before disabling the MPU in order to force
outstanding memory transactions.
The ARMv7-M documentation is less clear about that, and only specifies
that a DSB instruction followed by a ISB instruction must be used
before enabling the MPU, which is already the case. The ARMv7-M and
ARMv8-M MPU are relatively similar to believe the same sequence should
be used for disabling it.
This patch therefore adds a DMB instruction before disabling the MPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In Zephyr on Cortex-M SoCs with both the ARM MPU and the cache enabled,
there are 3 possible states and associated configuration for the RAM
cache attributes:
- MPU disabled WBWA non-shareable
- MPU enabled, background RAM region WBWA non-shareable
- MPU enabled, thread RAM region WBWA shareable
In practice this means than the thread RAM region toggles from
shareable to non-shareable on each context change.
However the Cortex-M7 SoC does not support the WBWA shareable
configuration and fallback to simpler caching configuration. The
Technical Reference Manual states:
"By default, only Normal, Non-shareable memory regions can be cached
in the RAMs. Caching only takes place if the appropriate cache is
enabled and the memory type is cacheable. Shared cacheable memory
regions can be cached if CACR.SIWT is set to 1."
Similar indications can be found in the documentation from various
vendors: ST (AN4838), NXP (AN12042) and Atmel (AN15679).
It means that the thread RAM regions are either not cached (CACR.SIWT=0,
default) or WBWT cached (CACR.SIWT=1). This causes a performance issue.
In addition before switching a region from cached to non-cached and
vice-versa, the existing MPU code does not perform cache clean and/or
invalidate operations. This might cause data loss or corruption.
We should therefore change the RAM cache attributes to make them always
consistent. This patches change the thread/application RAM region from
WBWA shareable to WBWA non-shareable. This is done for all ARMv7-M SoCs
with an ARM MPU, however other SoCs (M0+, M3, M4) do not have cache, so
their behaviour should be unchanged.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Move misc/Kconfig options to where they belong. misc/Kconfig was used as
a catch-all, but we are now able to put things in a better place.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add a new 'Kconfig tips and best practices' page that covers some
Kconfig best practices, tips, and arcana, like the following:
- What should be turned into a Kconfig symbol?
- Best practices and pitfalls for 'select'
- Factoring out common dependencies
- Kconfig shorthands
- Redundant defaults
- Explanations of various more obscure Kconfig features, like 'imply',
optional prompts, optional choices, and 'visible if'
Link the new page in the sidebar (under Developer Guides), the
application development primer, and the architecture and board porting
guides.
Perhaps other, more Zephyr-specific information could be added later on
as well, but this is a good start.
Include some other Kconfig-related documentation improvements as well:
- In the application development primer, give 'CONFIG_FOO=n' as the way
to set a bool symbol to 'n', instead of '# CONFIG_FOO is not set'.
That seems to be what people usually do in practice in Zephyr.
Explain why '# CONFIG_FOO is not set' works as well. There's a
technical reason for it, related to Make.
- Mention that the recommended syntax for referencing environment
variables is now $(FOO) (which uses the Kconfig preprocessor)
- Mention that the kconfiglib.py docstring has more in-depth
information about how symbol values are calculated.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
CONFIG_ADC_QMSI and CONFIG_ADC_QMSI_SS aren't defined anywhere so
remove the dead CMake references to them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CONFIG_ADC_DW_REPETITIVE and CONFIG_ADC_DW_DUMMY_CONVERSION aren't
defined anywhere so remove the associated code for these Kconfig
symbols.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
