If an aliases already exists in the defs we should filter it out. Also
if an alias exists in the new_def we should filter the alias out.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When Zephyr was building the C implementation of KConfig it used the
build script 'FindRegex.cmake' to satisfy a regex dependency.
Now that we no longer use the C implementation of Kconfig we no longer
use this build script, and it is safe to remove it.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Currently, when usb_dc_ep_write is called, data is copied to the
internal buffer, hence the requirement for fragmentation, regardless
of low-level nrfx_usbd driver. This commit forces the fragmentation
and prevents potential internal buffer overflow. Adittional
fragmentation flag was added to prevent triggering status stage
(it is handled by hardware completely on nRF chips).
Fixes#12339
Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
The msg->prev_addr is already stored in frnd->clear.frnd, so there's
no need to have an extra stack variable for this (in the form of
prev_addr).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use fixed-width type instead of enum for field op in struct
ticker_user_op to avoid struct layout differences between
compilers. Also make check whether struct sizes match size definitions
build-time asserts.
Signed-off-by: Wolfgang Puffitsch <wopu@oticon.com>
Increase the size of the MCUBoot flash partition in the fstab-debugger
partition table, to accommodate for the RTT console and logs.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
The MCUBoot partition in the default partition table (fstab-stock)
is not meant to accommodate an RTT console, since the board does
not have a SEGGER chip.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Since `str` is the output buffer, `bt_hex_real` should limit its output
length according to the `str` size, not the `hex` size.
Signed-off-by: Jiahao Li <reg@ljh.me>
net_buf_linearize() used to clear the contents of output buffer,
just to fill it with data as the next step. The only effect that
would have is if less data was written to the output buffer. But
it's not reliable for a caller to rely on net_buf_linearize() for
that, instead callers should take care to handle any conditions
like that themselves. For example, a caller which wants to process
the data as zero-terminated string, must reserve a byte for it
in the output buffer explicitly (and set it to zero).
The only in-tree user which relied on clearing output buffer was
wncm14a2a.c. But either had buffer sizes calculated very precisely
to always accommodate extra trailing zero byte (without providing
code comments about this), or arguably could suffer from buffer
overruns (at least if data received from a modem was invalid and
filled up all destination buffer, leaving no space for trailing
zero).
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The information message when processing the yaml files is
cryptic when there is an override. This change adds filenmae
of yaml file being processed and the parent tuple with
the override.
Signed-off-by: David Leach <david.leach@nxp.com>
Currently, when handling a Friend Request message with `prev_addr` set,
we look up existing friend entry using `prev_addr` as the address.
However, `prev_addr` is the address of the requesting node's previous
friend, NOT the address of the requesting node itself. Therefore, we
should always look up existing friend entry using `rx->ctx.addr` as the
address.
Signed-off-by: Jiahao Li <reg@ljh.me>
Provide a dtsi file that sets up common capabilities for all
Feather-based Particle Mesh devices. Provide additional dtsi files for
some obvious peripheral options.
Remove the xtensa esp32 image: it didn't build, and there's no
indication of how the ESP32 firmware can be updated on the Argon board.
Use particle_argon as the nRF52840 side of the board.
Add Particle Boron support.
Note that dtsi files must be replicated in each board directory until
tooling supports DTS includes from a shared area.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
pyocd recently merged its command-line tools into a unified pyocd tool
with subcommands. The separate command-line tools still remain, but are
deprecated. Update the pyocd version required by zephyr in preparation
for updating the pyocd runner to use the new unified tool commands.
Pin pyocd to a specific version rather than allowing any version greater
than or equal to 0.14.0 because there have been a few unstable releases
recently. Version 0.14.3 is what I have been using locally and know to
be stable.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This partially reverts commit 5a47c60dbf.
The soc.h is now only included when _soc_irq_*() is being referred.
Fixes#11077.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
These two tests are hitting a stack overflow on x86_64 (not entirely
surprisingly), but can't just increase stack size because there is an
assert in the CMSIS compatibility layer that stacks be under 512
bytes. Just disable for now.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This builds with a host compiler, not one from the SDK, and so no
newlib library is available. There is work to enable newlib detection
at and above the cmake level. This patch can be reverted when that
lands.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is actually nothing wrong with this test code idiom. But it's
tickling a qemu emulator bug with the hpet driver and x86_64[1]. The
rapidly spinning calls to k_uptime_get_32() need to disable
interrupts, read timer hardware state and enable them. Something goes
wrong in qemu with this process and the timer interrupt gets lost.
The counter blows right past the comparator without delivering its
interrupt, and thus the interrupt won't be delivered until the counter
is next reset in idle after exit from the busy loop, which is
obviously too late to interrupt the timeslicing thread.
Just replace the loops with a single call to k_busy_wait(). The
resulting code ends up being much simpler anyway. An added bonus is
that we can remove the special case handling for native_posix (which
was an entirely unrelated thing, but with a similar symptom).
[1] But oddly not the same emulated hardware running with the same
driver under the same qemu binary when used with a 32 bit kernel.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This architecture doesn't support stack canaries. In fact the gcc
-fstack-protect features don't seem to be working at all. I'm
guessing it's an x32 ABI mismatch?
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This is intended to be a value set by the platform to adjust the size
of stacks created by tests. This test was setting it explicitly, and
failing to honor it when creating its own stacks.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
No MPU support there yet. This test should really be predicated on a
kconfig variable, not architecture.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When tickless was disabled, this inverted test would never fire the
first interrupt and the timer would be silent. Just remove it.
There's no harm in unconditionally enabling a single timer interrupt
at boot.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The call to _arch_switch is a giant screaming sign inviting optimizer
bugs. The code that appears before is what happened long ago when we
were switched out, but the version that EXECUTED just now is actually
in a different thread. So the assignment to _current before the
switch actually assigned OUR thread (the "new_thread" of the old
context!) to _current.
But obviously the optimizer looks at that code and assumes that the
_current which got assigned to the thread we were switching to long
ago is still correct, and used it when retrieving the swap return
value.
Obviously the real bug here is that the _arch_switch() in question
lacked a memory clobber (and it's getting one).
But we can remove two lines, remove code from inside the interrupt
lock and make the implementation more robust by moving the read to
after the irq_unlock() (which generally also has a memory clobber).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Host toolchains don't tend to provide an x32 libgcc. But we don't
actually need one for existing code. This is fragile, but better to
work for all but obscure cases than break outright.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
It's worth using custom timing information on a few systems to save
cycles or gain precision. But make the use of k_cycle_get_32() a
proper default instead of hardcoding all the platforms and failing to
build on new ones. On Xtensa and RISC-V (and now x86_64) the cycle
informatoin from that call is a very fast wrapper around the native
counters anyway -- all you would save would be the function call
overhead.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These files were relying on _thread_essential_set() from
kernel_internal.h, but not including it directly. New architectures
won't transitively include things the same way.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
I was half way through typing up my own one of these when I realized
there was one already in the tree. Move it to a shared header.
(FWIW: I really doubt that most architectures actually benefit from
their own versions of these tools -- GCC's optimizer is really good,
and custom assembly defeats optimization and factorizations of the
expressions in context.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The HPET default is to deliver events on the same INTIn as the legacy
PIT IRQ, and in fact our code requires that because it uses the
"legacy routing" option. So this isn't really a configurable and has
to be set correctly. Do it right in the kconfig default instead of
forcing boards to set it.
(No, I have no idea where "20" came from either.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was apparently intended to allow for per-arch linker includes,
but no such includes ever existed. All it does is senselessly throw
an error on unrecognized architectures. Yank.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These files were using z_thread_malloc() without including
kernel_internal.h. On existing architectures that works due to
transitive includes, but x86_64 has a thinner include layer and
doesn't do it for us. Include the files required for the APIs we use.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix the QSPI and hyperflash nodes to be proper SPI children and expose
the address range for direct access as part of the controller's reg
region.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We need to refactor how we determine CONFIG_FLASH_{SIZE,BASE_ADDRESS}
for when we have a QSPI that is memory mapped. "zephyr,flash" is going
to point the actual flash component that will be on a SPI bus and thus
the device node's reg property tells us which CS on the SPI bus its on,
not the memory mapped address/size of the flash.
So we make a few assumptions to handle this case:
1. If the #size-cells for the flash node is 0, we assume its a QSPI
memory mapped flash
2. That the QSPI memory mapped node (parent of what "zephyr,flash" is
point to, will contain a reg propery where the second reg pair will
be the memory mapped region for the flash.
We move handling of CONFIG_FLASH_{SIZE,BASE_ADDRESS} into flash.extract
so its all in one place.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Make the documentation page a little bit more interesting with top-level
navigation grid highlighting the most important sections with a brief
description.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add Accelerometer mouse by using fxos8700 accelerometer and using data
to control USB HID mouse.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
move development model from the wiki to the main documentation to keep
it in sync and updated all the time and to get proper reviews.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
