Fix the control procedure context safety by adding checks in
thread mode control path to detect pre-emption by interrupt.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This is a squash merge of commits introducing the new split
Upper Link Layer and Lower Link Layer architecture of the
Bluetooth Low Energy controller.
This introduces a new, improved Link Layer based on the
concept of split responsibilities; The Upper Link Layer
(ULL) is in charge of control procedures, inter-event
scheduling and overall role management. The code for the
ULL is shared among all hardware implementations. The
Lower Link Layer (LLL) is responsible for the intra-event
scheduling and vendor specific radio hardware access.
The communication between ULL and LLL is achieved through
a set of FIFOs that contain both control and data packets.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Wolfgang Puffitsch <wopu@oticon.com>
Signed-off-by: Morten Priess <mtpr@oticon.com>
Preliminary work done towards Mesh extensions on the old LL
architecture implementation.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Missing updates to old architecture implementation towards
introduction of new ULL LLL architecture.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Refactored the internal LL interfaces to have return value
to match the HCI error code u8_t data type.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
The help text has been stating that CONFIG_STACK_CANARIES will
silently be ignored when the compiler does not support them. But this
is not the desired behaviour of CONFIG_STACK_CANARIES[1].
This patch corrects the help text to state that an error will occur if
this feature is enabled, but not supported.
[1] "I would much rather see the build break if someone tries to
enable the stack canaries, and the compiler doesn't support
it. Because what happens now is that if someone enables this option,
and there is no support, the build will succeed but there are no
actual stack canaries in place, and unless the user is paying close
attention to the cmake test output they will have no idea."
--
https://github.com/zephyrproject-rtos/zephyr/issues/5019
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This re-write fixes several issues with how we were checking for
compatibility with the canary flags:
If a compiler did not support any stack canaries, but a user had still
enabled them, this would silently result in no canaries being added
instead of error-ing out as it should have.
Compatiblity for '-mstack-protector-guard=global' was unnecessarily
being tested twice, once in 'check_c_compiler_flag' and once in
'zephyr_cc_option'.
Compatibility was being tested with 'check_c_compiler_flag' which is
slower than 'zephyr_check_compiler_flag' because it does not cache
it's results.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Put the kernel overview at the top level of the kernel documentation and
make it visible immediatly when browsing the kernel docs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added tests for async UART API and test configuration for
nrf52840_pca10056 board.
For tests to work, RX and TX pins have to be connected together
and second UART is needed to output results to console.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Added new UART API, that allows for longer transmissions, leaves
IRQ handling on driver side and allows for DMA usage.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
Number of USB endpoints is set via DTS, nevertheless USB driver
tries to enable all endpoints as it uses number of endpoints from
nRFx.
This commit makes driver enable only these endpoints that were
enabled in DTS.
Signed-off-by: Pawel Dunaj <pawel.dunaj@nordicsemi.no>
Add support to STM LIS2DS12 3-axis accelerometer driver.
The driver support I2C and SPI bus communication and both
polling and drdy trigger mode.
Currently it uses high resolution only as power mode.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Enables the mcux ethernet driver and pin muxes on the mimxrt1020_evk
board, the same way it is done on the mimxrt1050_evk board. Updates the
board documentation and yaml supported list accordingly.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by
the ARM core) or if the ENET device is enabled.
The 500MHz clock should be enabled if the SoC is the MIMXRT1021.
The ENET clock should be enabled if the ENET device is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Kconfig currently emits a warning when building for a MIMXRT1021 SoC:
warning: INIT_ENET_PLL (defined at
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052:66) has direct
dependencies NET_L2_ETHERNET && SOC_MIMXRT1052 && SOC_SERIES_IMX_RT
with value n, but is currently being y-selected by the following
symbols:
- SOC_MIMXRT1021 (defined at soc/arm/nxp_imx/rt/Kconfig.soc:12),
with value y, direct dependencies <choice> (value: y), and select
condition <choice> (value: y)
This is due to the fact the ENET PLL is the one used by the ARM core on
the MIMXRT1021 so it is always enabled, while it is declared protected
by NET_L2_ETHERNET and SOC_SERIES_IMX_RT.
Fix that by declaring the symbol in Kconfig.defconfig.series.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAM E70 Ethernet driver uses scatter gather DMA to transmit data.
Each fragment of a network packet is mapped from a set of descriptors
that is used by the controller to do the DMA transfer. Each descriptor
contain an address and a length/status. The important status bits are
GMAC_TXW1_LASTBUFFER to indicate the last fragment of a packet and
GMAC_TXW1_USED to indicate that a descriptor has been processed by the
controller.
When starting a transmission, the controller start at the descriptor
after the last one that has been processed. If the descriptor is NOT
flagged by GMAC_TXW1_USED, it sends a first packet by sending all the
fragments up to a descriptor flagged with GMAC_TXW1_LASTBUFFER. The
first descriptor of a packet *and only the first descriptor of a packet*
is then modified to flag it with GMAC_TXW1_USED and to provide a status
(mostly related to errors and checksum offloading). It then continues
with the next packet and so on and only stops if the next descriptor
after GMAC_TXW1_LASTBUFFER is flagged with GMAC_TXW1_USED.
Therefore in order for the controller to stop processing descriptors,
the strategy is to flag the next descriptor after the last fragment to
be sent with GMAC_TXW1_USED. When the next packet has to be queued, the
flag can be removed before starting a transmission.
This is what is currently done in the current driver. However there is a
small race condition in the implementation: if packets are queued fast
enough, the controller is still sending the fragment of the previous
packet when the descriptor are written. When writing the first
descriptor, the GMAC_TXW1_USED flag is removed. This is done after
writing the address (with a memory barrier) so that looks safe. However
given that the GMAC_TXW1_USED flag is only added by the controller to
the first descriptor of a packet it means the next descriptor might
have it cleared. In that case the descriptor is processed, and a junk
packet is sent. That also desynchronize eth_tx and tx_complete as one
or more packets than expected are transmitted.
In order to fix that the strategy is slightly changed to initially write
the first descriptor with the GMAC_TXW1_USED flag set. Once all the
descriptors from the packet are written the bit is cleared (after a
memory barrier). Then the transmission can be started safely.
The patch also does a small optimization writing the next descriptor
with only the GMAC_TXW1_USED bit set instead of setting this bit. As
this will be a non-cached area, it's better avoiding a read followed
by a write if not necessary.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
If a pkt has more frags than the number of TX descriptors, we end up in
a deadlock situation, as the whole packet and thus all the frags have to
be mapped in the descriptors at once. That is why the number of
descriptors is defined as CONFIG_NET_BUF_TX_COUNT + 1.
This wrongly assumes that only TX buffers can be used to send data,
however the packets might also come from the RX buffers, like for
example with ICMPv4.
Therefore define the number of descriptors as the maximum of
CONFIG_NET_BUF_RX_COUNT + 1 and CONFIG_NET_BUF_TX_COUNT + 1. This fixes
a deadlock when CONFIG_NET_BUF_TX_COUNT is much smaller than
CONFIG_NET_BUF_RX_COUNT.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The current SAM E70 Ethernet driver sometimes get stuck if the stack
has to send 2 packets in a row, for example an ack for the just received
data + answer data.
The problem is the following one:
1) The first packet goes through eth_tx, one tx_desc_sem semaphore is
taken, and the tx_timeout_work delayed work is submitted.
2) The second packet also goes through eth_tx, another tx_desc_sem
semaphore is taken, and the tx_timeout_work delayed work is not
started because there is already one already submitted.
3) The first packet has been sent, one tx_desc_sem semaphore is given
and the tx_timeout_work delayed work is cancelled.
4) The second packet has been sent but given the delayed work has
already been cancelled, tx_completed is not called: the tx_desc_sem
semaphore is not given back and the network packet is not
unreferenced.
The whole timeout concept probably has to be reworked. In the meantime
it is probably better to just drop the timeout code instead of keeping
the driver broken. We can only get stuck on the TX path if there is a
bug in the driver or a hardware malfunction. It might happen, but with
the less probability then the current hangs. In addition it just hides
the real issues and prevent them to be fixed.
This commit therefore just remove the timeout code in the TX path.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
mbedTLS benchmark used 32-bit arithmetics for time calculations
(nanosecond resolution), which could overflow on slower platforms
on more time-consuming benchmark tests. In result, the benchmark
could give incorrect timing information. Using 64-bit arithmetics
prevents this issue.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup dependencies in Kconfig and convert some top-level options to
menuconfig. guard all dependent options with if instead of using
'depends on' for readibility.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
lib/ was starting to get messy and inconsitent. Files being either
dumped in the root or in sub-directories without a clear plan.
Move all library components into one single folder and call it 'os'.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We have dependency on this module in code which is part of Zephyr. When
this module is split out of the tree we need to be able to build. Move
this Kconfig part to be part of zephyr and keep the external code in
ext/ with plan to split it out on the future.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Extend generic mbedTLS configuration file with MBEDTLS_AES_ROM_TABLES
option. This allows to save some RAM (~8kB) in favour of ROM and
performance.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Running sanitycheck from Windows is not supported yet. Unfortunately,
the error message is obscure when a user is unaware of this and runs
it from Windows anyway.
This patch gives an easy to understand error message explaining this
issue.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Out-of-tree doc builds rely on extract__content.py to copy needed
content from the source folders to the build folders. To minimize what's
copied, all the reST files are copied plus files referenced by the reST
files. The extract_content.py script does a pattern match scan for
directives that reference other files (e.g., .. image::) and copies the
referenced file. It's not a smart parser though and doesn't ignore
directives in comments or in code-blocks. Rather than teaching the
script how to properly parse reST files, we'll just change the example
(in a code-block) to reference an existing image.
Fixes: #12621
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
It was reported, and confirmed by multiple parties that default
CONFIG_ETH_MCUX_RX_BUFFERS=2 under some packet load leads to
1s and increasing packet processing delay and eventual deadlock.
No reports were about CONFIG_ETH_MCUX_TX_BUFFERS=2, but be on safe
side and just set that to the minimal value as the current default,
to allow us to have good conservative base to test various networking
stack issues.
Fixes: #3132
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Correct it so that it is possible to use PWMs on nRF9160 as well,
not only on nRF5 family SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Minor adjustments are done to the nRF clock_control and rtc_timer
drivers to make them usable on nRF9160 as well.
The arm_irq_vector_table test code is modified only because it uses
the function that has been renamed in the nrf_rtc_timer driver.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use the symbol generated from DT so that it is common for nRF9160
and nRF5 family SoCs. To avoid artificial renaming of CLOCK_POWER_IRQn
to POWER_CLOCK_IRQn.
For nRF5 family SoCs clock nodes were not defined so far, thus they are
added so that the proper DT symbol is generated for them as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add the header file with the nrfx drivers configuration suitable for
the nRF9160 SoC. This file contains also definitions of CMSIS symbols
(like NRF_CLOCK or NRF_SPIM0) for structures of peripheral registers.
These symbols are used in nrfx HALs and drivers, and for other nRF SoCs
they come from MDK files. For nRF9160 they need to be mapped to proper
addresses in Secure or Non-Secure domain, so we use the information
coming from DT to get it done automatically.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add missing node for instance 0 of the RTC peripheral and use an alias
to the flash-controller node instead of the nvmc node definition (there
is no need to have a separate node just to get the NVMC base address).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
