Add SPI_6 Kconfig symbol as this is the higher supported instance on
STM32.
This makes symbol CONFIG_SPI_6, used in stm32 driver a valid symbol.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit enforces default double-word stack alignmnet
on exception entry for Cortex-M3 and Cortex-M4 MCUs. The
patch ensures that we have consistent behavior in all
Cortex-M MCUs (double-world stack alignment on exception
entry is enforced by default in ARMv6, ARMv8, and Cortex-M7
processors).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit updates the documentation of Kconfig option:
STACK_ALIGN_DOUBLE_WORD for Cortex-M microprocessors, stating
that the option is used in ARMv7-M MCUs to enforce 8-byte
stack alignment upon exception entry.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
A few cases were missed where we weren't cleaning up the existing
connection correctly. This was easily missed because we try and
clean up the connection everywhere.
Instead, let's clean up any existing connection prior to starting
a new one in the do_bootstrap_reg() and do_registration()
functions.
Signed-off-by: Michael Scott <mike@foundries.io>
- Fix enum naming throughout
- Correct next_instance logic
- Move to registration server if no bootstrap server is found
- Fixes to logging
Signed-off-by: Michael Scott <mike@foundries.io>
use cmsis functions to avoid using direct assembly for main thread
switching.
This patch uses cmsis functions to:
- set PSP(process stack pointer) to main stack
- enable interrupts
Fixes#12878
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
After including native_posix USB controller we can perform some simple
tests on native_posix.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
There is no need to rename the POSIX types, so let's not do it to
simplify things
Also remove an unnecessary guard (POSIX_ARCH) to avoid mystifying
this any more than necessary
Related to #13054
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
If an unitialized/zeroed optional attribute was passed to osThreadNew
the priority would be osThreadNone i.e. uninitialized. This causes an
ASSERT to be hit as the priority isn't valid (it is not between
osPriorityIdle and osPriorityISR).
The fix checks the passed in priority is not osPriorityNone and assigns
osPriorityNormal. This is the correct CMSIS behaviour.
The ASSERT will still be hit if the priority is invalid (<0).
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Fixed an issue whereby if an attribute structure was passed into a CMSIS
RTOS v2 'new' function with an invalid address i.e. NULL assigned to the
name (char*) member the memcpy at the end of each new function
would cause a segmentation fault i.e. read from an invalid
address.
This has been fixed by checking if the name is NULL and using the
default name from the init struct if it is. This is the same name
that would be used if not passing in the optional attr function
argument.
Changed the memcpy to strncpy to ensure that the copy does not read
beyond the end of the source string and changed the length from 16 to 15
(by means of a `sizeof(...)-1`) of the destination buffer to ensure that
it will always be nul-terminated.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Added a set of tests that use the default thread stacks to ensure they
work the same as the passed in stacks. Abstracted the common
functionality into functions.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Implemented dynamic thread stacks for CMSIS threads by declaring an
array of default sized thread stacks. Allocation cannot be done on the
heap as some architectures require strict alignment for stacks so the
macro must be used to define the stack to ensure most compatibility.
Added a Kconfig variable to limit the number of dynamic threads on the
system (they also count towards total CMSIS thread count). This is so a
developer can have fine grained control over how many dynamic threads
can be allocated because all their stacks must be allocated up front so
could use a lot of memory needlessly if oversubscribed. The default
value is 0 which effectively disabled dynamic threads but also reduces
the memory impact to almost none.
Fixed an assert bug where thread_num was being tested against the
maximum allowed CMSIS threads - it previous checked for less than or
equal which actually (due to when the increment happens) allowed there
to be one more thread. The check now correctly uses less than and only
allowed up to the defined maximum.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Implemented a second set of memory pool tests that function on a
dynamically allocated memory pool. Abstracted some of the common
functionality to a common function.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Implemented dynamic allocation of memory pools in a similar to manner to
what was already implemented for message queues. Added all the same
checks on size vs. maximum allowed and current heap.
Added an additional Kconfig variable to define the maximum size of a
dynamically allocated memory pool.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Added some additional checks when creating a message queue to ensure the
size of the queue does not exceed the size of the buffer passed in via
the optional attributes.
Added a new Kconfig option to limit the maximum size of a message queue
dynamically allocated on the heap.
Added a check to ensure the heap is at least large enough to hold a
maximum size dynamically allocated queue.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
Added Kconfig dependency that NUM_PREEMPT_PRIORITIES must be at least
osPriorityISR (56). This was enforced by a build assert message but not
decribed in the Kconfig.
Signed-off-by: Carlos Stuart <carlosstuart1970@gmail.com>
The commit 77cb942a97 broke the generation of sw_isr_table for
multi-level IRQs. This patch fixes it.
Fixes#13082.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Enable the SPI driver on the HiFive 1
This makes the following configurations choices for the HiFive 1:
The SPI 0 peripheral driver is not enabled by default because it is in
charge of mapping the SPI flash into memory. This can be configured
using the CONFIG_SIFIVE_SPI_0_ROM KConfig option.
The SPI 1 peripheral driver is enabled by default and the pinmux is
configured for all of its outputs
The SPI 2 peripheral driver is enabled by default because it is present
in the DTS for the FE310, but because the QFN48 package used on the
HiFive 1 doesn't route those pins from the silicon die, the pinmux can't
enable the SPI 2 pins.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
The 0.10 version of the Zephyr toolchain supports building on the
openisa_rv32m1 SoC. So if the ZEPHYR_TOOLCHAIN_VARIANT is 'zephyr'
than select RISCV_GENERIC_TOOLCHAIN.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Expose ZEPHYR_TOOLCHAIN_VARIANT so that Kconfig can make choices based
on how its set. For example we RISCV_GENERIC_TOOLCHAIN if the variant
is 'zephyr'.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit enhances the power_mgr sample by adding code
presenting power state locking API as well as its effect
on the decisions made by the Power Management Policy.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit enables fine-grained power state locking.
Now, each power state could be independently enabled or disabled.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
add the handling of APP_SHARED_MEM.
privileged threads can access all the mem
explictly defined in user mode, i.e., APP_MEM & APP_SHARED_MEM
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Indicate that PWM is supported on several Nordic DK boards so that
the pwm_nrf5_sw and pwm_nrfx drivers are covered by CI builds.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enable HW PWM driver instead of the SW one on nRF SoCs where the PWM
peripheral is present.
Default PWM instances are also enabled on Nordic DK boards so that it
is possible to build the basic fade_led sample for them without extra
adjustments.
After the above changes are applied, some configuration alterations
in basic samples blink_led and fade_led become no longer needed.
These are removed. And the blink_led sample is corrected so that it
works with the nRF HW PWM driver as well.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch puts checks in place to ensure that callers to the k_mem_slab
APIs provide word aligned block sizes. If this is not done, this can
result in unaligned accesses and subsequent crashes.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This reverts commit eb6ea28649.
Reverting this to avoid confusion in using the gpio callbacks.
Fixes#11565
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
To avoid confusion, callbacks using ordinal pin numbers
is going to be reverted. So the driver has to be re-worked
to expose multiple devices so each device has 32 pins.
Also fixes#12765
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the shared_irq driver to be configured by device tree.
With previous implementation, only the board configuration can
override the IRQ trigger, as the trigger config is a "choice" rather
than "config". With this patch, the driver can be fully configued at
the SoC level.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch increases the amount of slab memory per item for the shell
history to match the maximum command input buffer size plus the
accounting information for the dnode list item.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
PAE tables introduce the NX bit which is very desirable
from a security perspetive, back in 1995.
PAE tables are larger, but we are not targeting x86 memory
protection for RAM constrained devices.
Remove the old style 32-bit tables to make the x86 port
easier to maintain.
Renamed some verbosely named data structures, and fixed
incorrect number of entries for the page directory
pointer table.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Those are outdated and unrunnable tests that require lots of
customization to keep them building and the information they provide
can't be retrieved in other means.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
