This is a rework of the 6lo IPHC. The compression now works inline
on the original buffer instead of allocation a new one.
Additionally DAM_11 (Destination address fully elided) has precedence
over DAM_10 (16 bit compressible) now.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The `start_udp_and_tcp` funcion is a blocking function, therefore it
should not be called from the system workqueue, as it would stall it.
Because it was called in such a way, the retry mechanism, which
also relied on the system workqueue did not work properly.
This commit fixes the issue, by keeping the main application processing
in the main thread, and using a semaphore to synchronize with the
connection manager.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Move CMake ExternalProject integration of OpenThread to the
CMakeLists.txt file within the OpenThread fork.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
zero slice_ticks when can't time slice so that next_timeout will
ignore slice_ticks of _current_cpu and system can stay low power
state longer time.
Fixes: #17368.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
For systems with userspace, the sys_sem exist in user memory working
as counter semaphore for user mode thread. The implemention of sys_sem
is based on k_futex. And the majority of the synchronization operations
are performed in user mode to reduce the calling of system call.
And for systems without userspace enabled, sys_sem behaves like k_sem.
Fixes: #15139.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
sw_isr_table has two entries, an argument and an ISR function. The
comment on struct _isr_table_entry in include/sw_isr_table.h says that
"This allows a table entry to be loaded [...] with one ldmia
instruction, on ARM [...]". Some arch, e.g. SPARC, also has a double
word load instruction, "ldd", but the instruct must have address align
to double word or 8 bytes.
This commit makes the table alignment configurable. It allows each
architecture to specify it, if needed. The default value is 0 for no
alignment.
Signed-off-by: Yasushi SHOJI <y-shoji@ispace-inc.com>
We don't generate any CONFIG_ prefixed symbols from dts files so we
don't need to try and import them in anymore.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code limited the length of a write to the size of a page,
but did not check whether the starting position was far enough into the
page that the write would still cross a page boundary.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The test assumes that the settings area is empty. This happens
naturally when the area is in the SOC flash and the chip flash is
entirely erased when the test is programmed. The test will fail if the
programmed board is reset and the test run again.
The test cannot pass by reprogramming when the storage area is in an
external flash device.
Make things repeatable for FCB by erasing the storage partition before
running the test.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
If the flash device is not configured, return an error rather than
dereferencing a null device pointer.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Particle mesh feather devices, and Nordic PCA10056, can both run
this example with the on-board JEDEC SPI NOR device if the driver
is enabled.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
There are multiple flash implementations. This sample was originally
written for the W25QXXDV driver, but has since been used for
jedec,spi-nor. The sample should work with multiple drivers.
Add device name sources for several drivers, falling back to spi-nor
which was recently used as a test filter.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Particle released documentation with a pre-release flash chip. Correct
the name to the actual as-sold device, and add the corresponding size
property as well as the has-be32k property. Also add an alias so we
can set partitions externally.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The driver historically used the erase block size (64 KiBy) as the page
size. There are other viable "sector" sizes, and for some applications
this one may be too large. Allow the application to specify the desired
flash page size.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The JEDEC API defines the hardware page, sector, and block sizes.
Deprecate the Kconfig settings, remove the `erase-size-block` property,
and add `has-be32k` to indicate that 32K-byte erase is supported.
Rework the driver to use the constants instead of configured values.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This commit adds the kernel.h include in order to provide
sys_clock_hw_cycles_per_sec() declaration.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The adc_stm32 driver used system timer frequency as a base for
busy-wait delay calculation. This commit corrects that by obtaining
the needed value from SystemCoreClock variable.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The wdog_cmsdk_apb driver used system clock frequency
as a base for timeout calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cc13xx_cc26xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_stellaris driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_qmsi driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_msp432p4xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cc32xx driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_pl011 driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The uart_cmsdk_apb driver used system clock frequency
as a base for baudrate calculation. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The spi_dw driver used system clock frequency
as a base for SPI bus frequency calculation.
This commit corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The log_backend_swo used system clock frequency
as a base for SWO clock calculation. This commit
corrects that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The clock control initialization code used system clock
frequency as a CPU clock frequency. This commit corrects
that by obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used timer clock frequency
as a system clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The SoC initialization code used system clock frequency
as a CPU clock frequency. This commit corrects that by
obtaining the needed value from DTS.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
