Errors has been ignored when using TLV writer to create/write object
instance/resources. Modify to propagate the error back to the caller.
To reproduce the issue, try to create IPSO light control object
instances twice. Since the default instance count is 1, the second one
should be rejected and responded w/ error. But the current
implementation will respond w/ 2.04.
Signed-off-by: Robert Chou <robert.ch.chou@acer.com>
We did not check the requested object/object instance/resource exists or
not before we adding an observer. Correct it by checking the existence
first.
Signed-off-by: Robert Chou <robert.ch.chou@acer.com>
We should stop sending out notification to the peer when the
object/object instances requested to be observed is removed
Signed-off-by: Robert Chou <robert.ch.chou@acer.com>
We were using sys_slist_remove() to remove object, object instance and
observer w/o passing the previous sys_snode_t to it (NULL).
This will instruct the function to treat the node as the list head and
result in unexpected behavior after the removal.
Correct it by using sys_slist_find_and_remove() or passing the previous
node to the function.
Signed-off-by: Robert Chou <robert.ch.chou@acer.com>
When a request demands to create a new object instance, it will search
whether the request object instance exists or not. However, current
implementation does not reset the lwm2m_engine_obj_inst at the time it
is deleted. It only removes the object instance from the sys list.
Correct the behavior by resetting both object instance and resource
instances at the time it's deleted. Also, consolidate function
lwm2m_delete_handler() and lwm2m_delete_obj_inst().
To reproduce the issue, try to create light control object instance
(/3301), delete the created instance and create it again. You shall find
following error message dumped.
> [ipso_light_control] [ERR] light_control_create: Can not create
instance - already existing: 0
> [lib/lwm2m_engine] [ERR] lwm2m_create_obj_inst: unable to create obj -
3311 instance 0
Signed-off-by: Robert Chou <robert.ch.chou@acer.com>
Currently, we don't have a .conf which enabled BT. This will be
re-enabled at some future date after migrating to the full net_app
APIs by setting CONFIG_NET_APP_BT_NODE=y.
Signed-off-by: Michael Scott <michael.scott@linaro.org>
- There's no point in building up "validity" (declared volatile for some
strange reason), just exit with false return value if any of the page
directory or page table checks don't come out as expected
- The function was returning the opposite value as its documentation
(0 on success, -EPERM on failure). Documentation updated.
- This function will only be used to verify buffers from user-space.
There's no need for a flags parameter, the only option that needs to
be passed in is whether the buffer has write permissions or not.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This will be used by system call handlers to ensure that any memory
regions passed in from userspace are actually accessible by the calling
thread.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We shouldn't be imposing any policy here, we do not yet use these in
Zephyr. Zero these at boot and otherwise leave alone.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
stm32f417xe and stm32f417xg have been introduced with 2
different defconfig files. Since same code is declared
in both files, mutualize declarations in a single file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove usart2_pins_b as this configuration is not possible
(PA15 could not be mapped on USART2).
Besides usart2_pins_c as this configuration is not used yet,
remove to reserve "usart2_pins_c" for future use
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Default configuration for USART1 (Console output) on board
stm32f3_disco was set on PA9/PA10, which matches Rev-A/B
configuration. Though, on more recent configuration of the
board (Rev-C onward). USART1 is mapped to PC4/PC5.
This configuration has the benefit to support VCP, hence it
is chosen to be set by default.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Enable BlueNRJ chip on disco_l475_iot1 board.
Communication with SoC, is done over SPI(3). Hence this
commit enables SPI3 on SoC and configure BT_SPI IRQ,
RESET and CS pins.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add SPI3 pin definitions for PC10, PC11, PC12.
This is required to use SPI3 on disco_l475_iot1 board
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add board configuration, dts and pinmux based on both
stm32f469i_disco board and nucleo_f412zg board
Signed-off-by: Massimiliano Cialdi <massimiliano.cialdi@powersoft.it>
Move all STM32 based board pinmux files into the board dirs so we are
consistent across all the STM32 platforms/boards.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fixes uart irq info in the device tree fixup files for frdm_k64f and
hexiwear_k64. They were incorrect in uart instance 5.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch enables I2C_2 support for 96b_carbon. Without
this patch, trying to build I2C_2 will result in build
error.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The enumerations stm32{f3,f4}x_pin_config_mode aren't used any
more. This patch removes them.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
TEMT is Transmitter Empty bit which is set only when the full FIFO
is empty. It makes sense to poll for THRE (Transmitter Holding
Register Empty) which is set when UART can buffer new character
for transmission (there is room in FIFO). This allows using the
FIFO in full.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
The LCR register specifies the format of the asynchronous data
communication exchange. Keep the data/stop bit and parity settings
intact during baud rate change.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
The byte ones are required for ns16550 uart driver which is
present on some arm socs. Add half-word ones for completeness.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If the packet is put pending because ARP request need to be
done, then do not unref original packet.
Fixes#1416
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Add a command "net arp" to net-shell. This new command will
print ARP cache contents if IPv4 and Ethernet are enabled.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
The commit 725be227 ("net/mgmt/event: Commands must be > 0 so
masking them works") prevented IPv6 address setting when an
application was initialized. The check in subsys/net/lib/app/init.c
needs to be adjusted because of that change.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
There were bunch of config options in tests/net, net-shell and
wpan_serial sample, and those options had wrong name so they
were ignored by the code.
Fixes#1428
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Doxygen-generated API documentation had the ability to
group API information into sections based on the class
of items: Defines, Typedefs, Enums, Functions and then
alphabetized with these groups. By removing the
Breathe directive :content-only: we can get these class
groupings back (instead of having items just sorted
alphabetically across all classes), and also allow @name
groups to be defined for creating and displaying additional
groups (as requested by a developer).
Depends on CSS changes in
https://github.com/zephyrproject-rtos/docs-theme/pull/14
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Doxygen comments for documenting structs have (known) issues,
and the Breathe addon for Sphinx used to create our API docs
has a known issue with forcing line breaks with @n or <br/>
This patch tweaks the comments to use a method used in i2s.h
to use @param comments for the members of a struct, and using
4 leading spaces (as done in i2s.h as well) to create a pre
block for the bit-field layout comments.
Fixes: #1415
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
In various places, a private _thread_entry_t, or the full prototype
were being used. Be consistent and use the same typedef everywhere.
Signen-off-by: Andrew Boie <andrew.p.boie@intel.com>
Indenting preprocessor directives reduces the code readability, because
it make preprocessor directives harder to spot.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
