In RISCV, stack always grows by a multiple of 16 bytes, even if we are saving
data of size < 16 bytes onto the stack.
Hence, for riscv32 architecture a bigger stack size is required for
test_mpool_concept, otherwise we experience stack overflow.
Change-Id: I938aa511efcae66f0131fa1bc23bd68600421885
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
When trying to build with newlib we get:
hci_driver.c: In function 'hci_driver_open':
hci_driver.c:389:10:
error: format '%d' expects argument of type 'int', but argument 2 has
type 'uint32_t {aka long unsigned int}' [-Werror=format=]
BT_ERR("Required RAM size: %d, supplied: %u.", err,
^
This is because we have different types for {u}int32_t between newlib
and mini-libc. We have to decide how we are going to handle this going
forward. Various options include use of PRIu32, making mini-libc match
newlib's types, disabling the -Werror=format, etc.
Change-Id: I5df8fa05dd7658e1f6b2eeb8fa84e3270f3dd208
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Enable gpio driver automatically when an app or upper
level driver needs it as chip select for spi.
Change-Id: I2bed134939426e2c84f313393d638a878c84fbfc
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
The pulse config option requires triggers enabled, so expand the
trigger requirement to also include all the pulse configs.
Change-Id: Ib94f4071cac757b24bfe940ca64fd11b07fed1c1
Signed-off-by: Bogdan Davidoaia <bogdan.davidoaia@linaro.org>
Introduce support to tag some issues as warnings, that can be printed
but not considered errors.
Added the ability to write the errors and warnings to split files, for
later reporting.
Added a more consistent help.
Change-Id: Ia75430c3337385afca59595437168ab643c92911
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
"struct k_mbox_msg mmsg" should be initialized before using.
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160083
Coverity-CID: 160470
Change-Id: I35714bf9d76723c5fdd8c2963bf76b42ae1b1867
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
assert should not contain "i++" which might work differently in a non-debug
build.
Coverity-CID: 160469
Change-Id: Id8fd50127dd93de1676b812ac0888c9ec2e1b5de
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
"int" value returned by k_mem_pool_alloc() should be checked.
Coverity-CID: 160471
Change-Id: I7ec19147e7a51997fed890075b06eba30bef9126
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This patch changes Quark SE power drivers to support multicore scenarios
e.g. both LMT and ARC core are enabled and manage power.
Handling LPS states in multicore scenarios are dead simple because LPS
states are core-specific states. It means that putting the LMT core in
LPS doesn't affect the ARC core, and vice-versa. DEEP_SLEEP state, on
the other hand, affects both cores since it turns power off from the SoC
and both cores are shutdown. It means that if LMT puts the system in
DEEP_SLEEP, ARC core is shutdown even if it is busy handling some task.
In order to support the multicore scenario, this patch introduces the
SYS_POWER_STATE_DEEP_SLEEP_2 state to both ARC and x86 power drivers.
On ARC, this state works as following:
1) Save ARC execution context;
2) Raise a flag to inform the x86 core that ARC is ready to enter in
DEEP_SLEEP;
3) Enter in the lowest core-specific power state, which in this case is
LPSS.
On x86, DEEP_SLEEP_2 is very similar to DEEP_SLEEP. The difference relies
in the post_ops() which calls _arc_init() in order to start ARC core so
it can restore its context.
This patch also adds the test/power/multicore/ directory which provides
sample application to x86 and ARC cores in order to easily verify the
multicore support. In test/power/multicore/README.rst you can find more
details regarding the applications.
Jira: ZEP-1103
Change-Id: Ie28ba6d193ea0e58fca69d38f8d3c38ca259a9ef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
"ret" returned from k_msgq_put() should be checked.
Coverity-CID: 160084
Change-Id: I192db3a67ab9489e8338f6636d4c2a6935e98d74
Signed-off-by: Sharron LIU <sharron.liu@intel.com>
This avoids asm files from having to explicitly define the _ASMLANGUAGE
symbol themselves.
Change-Id: I71f5a169f75d7443a58a0365a41c55b20dae3029
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
The K_<thread option> flags/options avaialble to users were hidden in
the kernel private header files: move them to include/kernel.h to
publicize them.
Also, to avoid any future confusion, rename the k_thread.execution_flags
field to user_options.
Change-Id: I65a6fd5e9e78d4ccf783f3304b607a1e6956aeac
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
They are internal states, not user-facing.
Also prepend an underscore since they are kernel internal symbols.
Change-Id: I53740e0d04a796ba1ccc409b5809438cdb189332
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
The execution_flags will store the user-facing states of a thread.
This also fixes a bug where K_ESSENTIAL was already assigned to
execution_flags via the options field of
k_thread_spawn()/K_THREAD_DEFINE().
Change-Id: I91ad7a62b5d180e09eead8985ff519809959ecf2
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
They are not part of the API, so rename from K_<state> to
_THREAD_<state>.
Change-Id: Iaebb7d3083b80b9769bee5616e0f96ed2abc5c56
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Unused.
Reuse bit for K_FP_REGS to keep the used bits the lowest possible.
Change-Id: I5998801ef34156271d4f66d1948a05e0b2ce58f7
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
This will be needed for some thread user options that will move to
kernel.h since they are part of the user API.
Change-Id: I46e302b6cafcdddbad3458134b98feb5b8d45d9b
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
When prio and sched_locked were moved into a struct together to create a
union with the combined preempt field, the volatile qualifier moved from
sched_locked to prio by mistake.
Change-Id: I5a8e01324f14e77e3d7162c12515471826023633
Signed-off-by: Benjamin Walsh <walsh.benj@gmail.com>
Changed README to RST and updated the formatting.
Jira: ZEP-1537
Change-Id: I012854daff6883cf462a3cc0246c73a8767dcd66
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Convert testcases to use the CMSIS NVIC APIs or direct NVIC register
access rather than the internal ones so we can remove them in the future.
Change-Id: I2a5a3eae713e66944cf105e7fffa603b88522681
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use the CMSIS NVIC APIs rather than the internal
ones so we can remove them in the future.
Change-Id: Ib9fe696e8d5e55f60865d3fd958a035135ce517a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use the CMSIS NVIC APIs rather than the internal ones
so we can remove them in the future.
Change-Id: I7bf3024ea4baf61f1e42bbbd5e4b0abfc6c04e6b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert driver to use the CMSIS NVIC APIs rather than the internal ones
so we can remove them in the future.
Change-Id: I31c2f37bc0aa35668a441f4ef2821b768dd7b817
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace _scs_relocate_vector_table with direct CMSIS register access and
use of __ISB/__DSB routinues. We also cleanup the code a little bit to
just have one implentation of relocate_vector_table() on ARMv7-M.
Jira: ZEP-1568
Change-Id: I088c30e680a7ba198c1527a5822114b70f10c510
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove use of __scs structures and defines in place of CMSIS defined
ones. Also, use __ISB() instead of inline asm.
Jira: ZEP-1568
Change-Id: I8798206a12680f6c50105c7c28112632ac9dde50
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CMSIS provides a complete implentation for reboot, we can utilize it
directly and reduce zephyr specific code.
Jira: ZEP-1568
Change-Id: Ia9d1abd5c1e02e724423b94867ea452bc806ef79
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().
Jira: ZEP-1568
Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.
We provide defaults in the case for:
IRQn_Type enum
*_REV define (set to 0)
__MPU_PRESENT define (set to 0 - no MPU)
__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
__Vendor_SysTickConfig (set to 0 - standard SysTick)
Jira: ZEP-1568
Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In preperation for removing the scb/scs layers and using CMSIS directly
lets remove all the _Scb* and _Scs* functions that are not currently
used.
Jira: ZEP-1568
Change-Id: If4641fb9a6de616b4b8793d4678aaaed48e794bc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
ARM's Cortex-M Prototyping System (MPS2) is a board with an FPGA that
can be programmed with different 'SoCs'. To use these in Zephyr we need
a set of board files for each variant.
This adds a board for a variant which implements a Cortex-M3 CPU; the
naming of this matches that used for the Zephyr SoC (which is itself
based on ARM's documentation nomenclature).
Change-Id: Ie02a67a03016b8aeee31e3694f0edbcc37f9ee64
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
ARM's Cortex-M Prototyping System (or MPS2) [1] is a board containing
devices such as RAM, ethernet and display, and at its heart there is an
FPGA which can be programmed with various 'SoCs' which implement the
CPU, SRAM, UARTs, SPI, DMA, etc. There are also software simulations of
systems based on this hardware which are part of ARM's Fixed Virtual
Platforms (FVPs).
All of the above could be regarded SoCs in the same series so we will
treat them as such in Zephyr.
In this initial patch we add SoC support for the public FPGA image
which implements a Cortex-M3 CPU, and includes definitions to support
use of the UARTs on this.
ARM's documentation for MPS2 images are titled 'Application Note ANnnn'
where the number nnn is different for each 'SoC'. E.g. Application Note
AN385 is for "ARM Cortex-M3 SMM on V2M-MPS2" [2]. The files ARM supply
for programming the board firmware also make extensive use of the ANnnn
nomenclature, so we will use this for the SoC name in Zephyr. E.g. the
Cortex-M3 SoC will be called 'mps2_an385'. Note, it is not possible to
use the CPU type (e.g. M3) for the name as there are multiple FPGA
images for some CPU types (e.g. there are three Cortex M7 images
with differing FPU and MPU support).
[1] https://www.arm.com/products/tools/development-boards/versatile-express/cortex-m-prototyping-system.php
[2] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0385c/index.html
Change-Id: Ice54f2d2cde7669582337f256c878526139daedd
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Now that we have a more generic mcux spi driver that can be used across
multiple Kinetis SoCs, remove the specific k64 spi driver.
Jira: ZEP-1374
Change-Id: Ifc324374f305837f5e3d2cfd7ad30d3608865b5b
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux dspi driver to adapt it to the Zephyr
spi interface. Unlike the existing k64 spi driver, this driver can be
used for other Kinetis SoCs that contain the dspi module.
Jira: ZEP-1374
Change-Id: I9417c1513565dfcc47ccda098492f60e840f4f84
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds default configurations for baud rate, transfer word size, clock
polarity and phase. These default configurations can be shared across
multiple spi drivers.
Change-Id: I221b402c075003014991b38f6342a89e55c3bec9
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add the GPIO pin and port definitions for the LEDs available on the
board.
Change-Id: I586a0ebfbbe8fa6e50dd1f91c1437665dd8ec677
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Add the GPIO pin and port definitions for the button and LEDs available
on the board.
Change-Id: If74cf9d780227346c7c8816e6eadca00b16953b2
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This patch updates the default defconfig in order to support the new
Timers implementation.
Jira: ZEP-1300
Change-Id: I749042bcf41c6b4cb11614315c3c2ce09cdb2aa8
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds Dualtimer support to be used as a Timer.
Jira: ZEP-1300
Change-Id: If13143c8a8bdb07210daca66deca44710a18406f
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds Dualtimer to be used as a counter.
Jira: ZEP-1300
Change-Id: Ic4a2d89ec7fc0c0c2a0bc7f6d32d97637049faaf
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds Timer 0 and 1 to be used as timers.
Jira: ZEP-1300
Change-Id: I57112a8ed6f5daa22345e8807e9ebe87bb09e782
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds clock control to the counters based on Timer 0 and 1.
Jira: ZEP-1300
Change-Id: I14499a833fe9720496ab7905bc1466e9b03bb316
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds the timers IRQ map to the ARM Beetle SoC platform.
Jira: ZEP-1300
Change-Id: If38a197210f71ae90c7ee6274395f064116faf72
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
