The function _new_thread sets the CALLINC for _thread_entry when calling the
new thread entry point. This should be CALLINC(1) (call4) instead of previous
one CALLINC(2) (call8).
This change allows resolving a crash when starting the first thread.
Change-Id: Ie97c95c87d1219342fed09f670fcae8a6230cefe
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Generally CPPFLAGS are applicable to all tools that use the C preprocessor.
Change-Id: I6dea9e39a20896550241f158190e03f7baadf471
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
XCC does not recognize __builtin_unreachable() and thus cause a link error.
Change-Id: I5dadf5a49d971d5e0a5ef88d582bb5ad2c36bced
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
These libraries are unlikely to be uesd by GCC port and thus should not be in
a generic make file. Moved to specific toolchain make file.
Change-Id: Ib585b87700e409d678f7a5cb60cff67b6022ab05
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
This is needed by next commit as some assembly files handling interrupts use
some options from this file.
This file is not included in next commit to separate code and build system
aptches.
Change-Id: Iff3a8019362599beb0c0058c3169480fa5183c1c
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
find_msb_set logic was wrong. find_lsb_set() is now an inline function.
Change-Id: I2c19540907723589298b2f6af2ce1d68704bf1d7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Master branch changed requirements for license headers while this
branch has been in development.
Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
XCC does not support compiler option -fno-defer-pop.
Change-Id: Ic47714331502b10e5e1e510984991615fe801696
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Provide generic support for running zephyr kernels on xtensa QEMU and
map D_233L SoC to dc233c QEMU core.
Change-Id: Ie804588f750213a7cc54dbc95c86ee4d62ba1ea5
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This platform is not a real board but let user handle the xtensa
simulator just like a board.
This is needed until a qemu like simulaotr is added to Xtensa.
Change-Id: I54ab28e86eea956cf85af3ee9b4a10f0d531e54d
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
Added arch sub folder, make files and Kconfig files for a set of standard SoCs.
Change-Id: I4ee9cba966860072e55c95795d87356b665e4d49
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
When test GPIO_INT_EDGE, there is no code to skip GPIO_INT_LEVEL
and jump to the end of the function. So GPIO_INT_LEVEL will
always be checked (Besides, it't always true), even if it's
testing GPIO_INT_EDGE, which will cause GPIO_INT_EDGE cases fail.
Add a goto statement for GPIO_INT_EDGE to skip GPIO_INT_LEVEL.
Jira: ZEP-1685
Change-Id: I10ce21c04c49f34aafdc2cd2f60f3e5377d6f1f5
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
This test case uses PWM0 port to test PWM on Quark Se.
However PWM0 port on Quark D2000 is initialized as tdo,
not PWM0 and disabling tdo will kill JTAG on D2000. So
use PWM1 and add PINMUX setting code to configure PIN_24
as PWM1 port, then the case will work on D2000 board.
Change-Id: Ib28d4750dac7396529388b781fb64bde048139d6
Signed-off-by: Qiu Peiyang <peiyangx.qiu@intel.com>
the commit test below adc driver api with different resolutions
and modes
adc_enable()
adc_read()
adc_disable()
move original adc test to adc_simple folder
Change-Id: I016b5e67a5d89fc8d5ae76f33799e5d3eb3e1cf8
Signed-off-by: jing wang <jing.j.wang@intel.com>
Remove tests that assert due to invocation from ISR which is not supported.
Change-Id: Idd2360847a467af6afdd9fbed8f87a620d9ed2f7
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The current I2C API provides inline functions to access 1 byte
register addresses. This commit adds a set of I2C inline functions
as shortcuts to handle:
- 16 bit register addressing. A family of functions that allows to
handle 2 byte register addressing and can receive the address
parameter as a simple variable. This allows a developer to handle
the address as a C constant or macro.
- Multiple byte addressing. A family of functions to access
registers with a configurable register address size. This family
of functions handle register addressing of any size but receives
the address parameter as a byte array.
Change-Id: Id369ab9eaad7eea807554371d3a520f67dc2e0f2
Signed-off-by: Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
Update the dma loop transfer sample app to use the new
dma api interfaces. This change is based on the api change
and the updated dma driver.
A RFC was posted recently on this.
Jira: ZEP-873
Change-Id: I289e2e08d4c775a833bf3d585d2706a903edd0bc
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
