Now states which are bound have single timer that means
means for lightness variation there is one timer & for
temperature variation there is one timer.
Signed-off-by: Vikrant More <vikrant8051@gmail.com>
Corrected mapping of message handler for Generic
Move Set, Generic Move Set Unack, Light CTL Set &
Light CTL Set Unack.
Signed-off-by: Vikrant More <vikrant8051@gmail.com>
Removed extra blank line. Add new
bound_states_transition_type_reassignment() function in
transition.c to improve code readability & understanding.
Signed-off-by: Vikrant More <vikrant8051@gmail.com>
This edition would improve by default mesh network
performance. This is after testing with nRFMesh app
from Nordic Semiconductor.
Signed-off-by: Vikrant More <vikrant8051@gmail.com>
Converts the adxl362 sensor driver to get the device name and spi slave
properties from the device tree rather than Kconfig. Updates the
build_all test accordingly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
According to the "USB Mass Storage Class" Spec. the serial
number shall contain at least 12 valid digits, represented
as a UNICODE string.
Fixes: #11336
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Include regex pattern matching of console output
to determine the sample execution status.
Add fixture to determine the hardware dependency
if any. If FRAM is connected to board externally,
then with fixture, automation would be able to
identify the board with sensor to trigger the
execution.
Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
Regex pattern matching is included to match the
execution log from console to return test result
in automation.
Also add fixture to identify the external sensor
connected for automation framework to trigger test
cases on particular board which is connected with
required sensor.
Signed-off-by: Spoorthi K <spoorthi.k@intel.com>
Support specifying a test fixture attached to a board to filter in/out
tests that require this fixture to be able to run a test.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In the MULTI_LEVEL_INTERRUPTS Kconfig we have a symbol for defining
the maximum IRQ per aggregator: MAX_IRQ_PER_AGGREGATOR
Instead of using a hard-coded value of 32 max irq per level,
let's use the value of MAX_IRQ_PER_AGGREGATOR
Signed-off-by: Michael Scott <mike@foundries.io>
If CONFIG_3RD_LEVEL_INTERRUPTS is not enabled then we see the following
error during sw_isr_table generation:
Traceback (most recent call last):
File "zephyr/arch/common/gen_isr_tables.py", line 291, in <module>
main()
File "zephyr/arch/common/gen_isr_tables.py", line 199, in main
if syms["CONFIG_3RD_LEVEL_INTERRUPTS"]:
KeyError: 'CONFIG_3RD_LEVEL_INTERRUPTS'
ninja: build stopped: subcommand failed.
Fix the logic to look for the symbol instead of referencing it.
Signed-off-by: Michael Scott <mike@foundries.io>
The following addition `depends on !(file in "ext")` allows
to exclude `ext/` warnings reported by coccinelle scripts.
Signed-off-by: Himanshu Jha <himanshujha199640@gmail.com>
We still have one platform using (for now) the pre-asm2 integration
where the timer interrupt was handled via custom assembly. It calls a
function named "_timer_int_handler" always, not the one we register
with IRQ_CONNECT.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The old xtensa layer had an unused/untested facility where it would
apparently try to slave a timer tick to an arbitrary interrupt. The
legacy headers were still checking the kconfigs used to enable that
even though nothing wants it and the new driver has removed them,
breaking builds on platforms like S1000 that still use the older
layer.
Don't try to finess this as these files are going away. Just make
them local preprocessor symbols and set them to the default values
they always had.
(Note: the feature doesn't sound like it would have been so bad,
actually. We should probably crib that idea of having an
"external_tick" driver, but there's no reason for it to have been
arch-specific.)
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Xtensa interrupts are handled generically, by testing a set of flagged
interrupts in the INTERRUPT register. It's not possible to know
exactly which device "caused" an interrupt.
The entry code was dispatching correctly, but it was failing to test
the enable state in INTENABLE. Such an interrupt will never "fire",
but it might still be flagged, and if we happen to end up handling an
interrupt of the same priority (due to some other device) the entry
handler would incorrectly invoke the disabled interrupt.
Found by dumb luck and a comedy of errors: the recent timer driver
change swapped the counter in use, which changed the interrupt number
to one shared with the I2C driver, whose early interrupts (odd that
this device is interrupting on boot when not in use, but whatever)
would then discover the OTHER timer counter had been flagged and try
to invoke an ISR for that other counter, which was the _irq_spurious()
spurious interrupt handler.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The firmware starts us with an already-initialized UART and a simple
ROM hook. Use that as the default printk handler so we can log in
very early boot. It will be overriden later (as it happens, by
another handler based on the same firmware hooks).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Architecture init code and/or HAL layers often have a working
"putchar" routine available long before the Zephyr driver layer is
initialized.
Make the default printk() output a weak symbol, so it can be
overridden on these platforms.
Also remove the kconfig depedency on CONSOLE_HAS_DRIVER, as this is a
non-driver mechanism.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
As explained in issue #8915 the STM32F4xx SoC family I2C
does not work well in Standard mode (100KHz). So let's
configure i2c3 in Fast mode (400KHz).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
This commit would add the pull-up or pull-down on the switch pin and
makes it functional on the board where there is no external pull-up.
Signed-off-by: Radoslaw Koppel <radoslaw.koppel@nordicsemi.no>
We should let drivers or board code include soc.h directly so we can keep
board.h to local info for board specific code.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
User mode may need to use this API to get a handle on
devices by name, expose as a system call. We impose
a maximum name length as the system call handler needs
to make a copy of the string passed in from user mode.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This driver is inspired from the w25qxxdv SPI NOR flash driver which was
already implementing the CFI (Common Flash Interface) for its purpose.
To handle other NOR flash a flash id table (as Linux do) which contains
the geometry for a few SPI NOR flash based on their JEDEC ID has been
introduced.
We currently support the following flash:
- W25Q80
- W25Q16
- W25Q32
- S25FL216K
- MX25UM512
The read and write functions are able to handle more then one page at a
time and return the number of bytes read or write.
Also because every NOR flash expect to disable the write protection
before writing or erasing, the write enable command is now part of the
write and erase functions.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
With the DT_ prefix change we missed adding prefixes in dts_fixup.h
on snps_emsk & snps_nsim for ARC_ICCM_0_BASE_ADDRESS and
ARC_ICCM_0_SIZE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Rewritten Xtensa CCOUNT driver along the lines of all the other new
drivers. The new API permits much smaller code.
Notably: The Xtensa counter is a 32 bit up-counter with a comparator
register. It's in some sense the archetype of this kind of timer as
it's the simplest of the bunch (everything else has quirks: NRF is
very slow and 24 bit, HPET has a runtime frequency detection, RISC-V
is 64 bit...). I should have written this one first.
Note also that this includes a blacklist of the xtensa architecture on
the tests/driver/ipm test. I'm getting spurious failures there where
a k_sem_take() call with a non-zero timeout is being made out of the
console output code in interrupt context. This seems to have nothing
to do with the timer; I suspect it's because the old timer drivers
would (incorrectly!) call z_clock_announce() in non-interrupt context
in some contexts (e.g. "expiring really soon"). Apparently this test
(or something in the IPM or Xtensa console code) was somehow relying
on that on Xtensa. But IPM is a Quark thing and there's no particular
reason to run this test there.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten driver along the lines of all the other new drivers,
implementing the new timer API. Structurally, the machine timer is an
up-counter with comparator, so it works broadly the same way HPET and
NRF do. The quirk here is that it's a 64 bit counter, which needs a
little more care.
Unlike the other timer reworks, this driver has grown by a few lines
as it used to be very simple. But in exchange, we get full tickless
support on the platform.
Fixes#10609 in the process (the 64 bit timer registers are unlatched
for sub-word transfers, so you have to use careful ordering).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Reworked using the older hardware interface code, but with an
implementation of the new API only. Much smaller & simpler.
As yet, tested (manually) only on a nrf52_pca10056 board.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
If this function is itself interrupted by a timeslice event, the
slicing state can be corrupted. Just re-use the scheduler lock
instead of using a new spinlock; this is a low-latency function that
won't deadlock. Found by inspection.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Rewritten along the lines of ARM SysTick. Implements only the new,
simplified API. MUCH smaller. Works with tickless pervasively. No
loss of functionality.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Many drivers won't need to implement z_clock_idle_exit() or
sys_clock_disable(). Make those weak stubs too.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Add a TICKLESS_CAPABLE kconfig variable which is used by the kernel to
select tickless mode's default automatically on drivers that support
it (rather than having to set the default per-board). Select it from
the ARM SysTick and Intel HPET drivers.
Also remove the old qemu_cortex_m3 default settings which this
replaces.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This test was written with an outrageously long timeout of 25 seconds.
That blows right through the 32 bit cycle counter on qemu_cortex_m3[1]
and produces an essentially random delay instead of the desired
number, causing a hang with the new SysTick driver in tickless mode.
Push the number down so it doesn't overflow. The root cause, though,
is that k_busy_wait() can take arguments it can't handle. It ought to
have an outer loop or something so that it can spin for INT_MAX
milliseconds correctly.
[1] Which has a 12MHz clock rate. Many hardware implementations are
much faster still.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
When TICKLESS_KERNEL is enabled, the current time in ticks is based on
a hardware counter and not interrupt delivery (which is the whole
point of tickless), so irq-locking does not prevent time from
advancing. Disable this test in that configuration.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
