Commit graph

7 commits

Author SHA1 Message Date
Nicolas Pitre c81d95b9ae riscv: FPU trap: test case thread typo fix
Need to wait for both threads.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2024-05-10 11:38:57 +03:00
Gerard Marull-Paretas 6810a53297 twister: s/riscv(32|64)/riscv
Only riscv is supported now, any 32/64-bit requirements need to use
CONFIG_64BIT now.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-02-26 12:49:06 +01:00
Nicolas Pitre 171cecb1d6 riscv: FPU trap: test case comment typo fix
Test case comment typo fix.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-11-13 09:51:34 +01:00
Nicolas Pitre 38373aa599 riscv: FPU trap: catch fused multiply-add instructions
The FMADD, FMSUB, FNMSUB and FNMADD instructions occupy major opcode
spaces of their own, separate from LOAD-FP/STORE-FP and OP-FP spaces.
Insert code to cover them.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-11-10 10:39:28 +01:00
Anas Nashif 345735d0a8 tests: remove CONFIG_ZTEST_NEW_API in all tests
Remove all usage of CONFIG_ZTEST_NEW_API from tests and sample as this
is now enabled by default.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-10-20 15:04:29 +02:00
Gerard Marull-Paretas 93b63df762 samples, tests: convert string-based twister lists to YAML lists
Twister now supports using YAML lists for all fields that were written
as space-separated lists. Used twister_to_list.py script. Some artifacts
on string length are due to how ruamel dumps content.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-05-10 09:52:37 +02:00
Nicolas Pitre 373f8acaa7 tests: riscv: test FPU sharing access behavior
The RISC-V FPU context switching code is intricate and sometimes subtle.
Here's a test that exercizes various code paths to ensure they work as
intended, and to confirm that the target hardware does behave as
expected too.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-01-30 23:47:36 +00:00