Commit graph

18 commits

Author SHA1 Message Date
Yong Cong Sin 3998e18ec4 arch: rename all esf struct to struct arch_esf
Rename every architecture's esf struct to `struct esf`.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-06-04 14:02:51 -05:00
Aleksandar Cecaric 0144ed6b63 arch: riscv: update coredump for 64BIT RISCV
Add RISCV 64bit registers and parse them in coredump script.

Signed-off-by: Aleksandar Cecaric <aleksandar.cecaric@nextsilicon.com>
2024-04-13 07:03:23 -04:00
Daniel Leung a819bfb2d5 xtensa: rename z_xtensa to simply xtensa
Rename the remaining z_xtensa stuff as these are (mostly)
under arch/xtensa.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-12-13 09:41:24 +01:00
Daniel Leung b4da11f929 gdbstub: xtensa: add support for dc233c core
This adds support for using coredump with Xtensa DC233C core,
which are being used by qemu_xtensa and qemu_xtensa_mmu.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-09-27 19:30:15 -05:00
Roberto Medina 6622735ea8 arch: arm64: add support for coredump
* Add support for coredump on ARM64 architectures.
* Add the script used for post-processing coredump output.

Signed-off-by: Marcelo Ruaro <marcelo.ruaro@huawei.com>
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Signed-off-by: Roberto Medina <roberto.medina@huawei.com>
2023-07-03 09:32:26 +02:00
Lucas Tamborrino eb028ccf55 debug: coredump: xtensa: Add esp32s3
Add coredump support for esp32s3.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Lucas Tamborrino ba3766a75f debug: coredump: xtensa: add esp32s2
Add coredump support for esp32s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Lucas Tamborrino fbbb82d6ac debug: coredump: esp32: Fix registers index for current toolchain
The current toolchain version for espressif SoCs does not
have the same limitation on registers indexing as the previous
one, enabling sending the correct A0-A15 register values directly

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Lauren Murphy 318e6db239 debug: coredump: add xtensa intel adsp, support toolchains
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.

Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.

Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2022-06-23 15:44:45 -04:00
Mark Holden d04ab82943 coredump: adjust mem_region find in gdbstub
Adjust get_mem_region to not return region when address == end
as there will be nothing to read there. Also, a subsequent region
may have that address as a start address and would be a more appropriate
selection.

Signed-off-by: Mark Holden <mholden@fb.com>
2022-05-10 15:26:31 -04:00
Mark Holden eba9c872b1 coredump: Add callee registers to arm arch block
Add version 2 to coredump arm_arch_block
which includes callee registers

Signed-off-by: Mark Holden <mholden@fb.com>
2022-04-13 13:26:37 -07:00
Lauren Murphy ddfb3a193c debug: coredump: dummy window registers, assign an to arn
GDB server dummies WINDOWBASE to 0 and WINDOWSTART to 1
for both arches and sends An as corresponding ARn for ESP32
to get around packet size limitation. Fixes backtrace and
other issues causing GDB client to crash.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2021-12-14 07:40:55 -05:00
Lauren Murphy 80927cac87 debug: coredump: add xtensa coredump gdbserver
Adds support for Xtensa to coredump custom GDB server for
the sample_controller and ESP32 SOCs.

Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
2021-12-14 07:40:55 -05:00
Mark Holden 1a697ccf59 coredump: add support for RISC-V
This adds the necessary bits in arch code, and Python scripts
to enable coredump support for RISC-V

Signed-off-by: Mark Holden <mholden@fb.com>
2021-12-08 08:54:32 -05:00
Daniel Leung 1387e7c7c2 scripts: coredump: fix crashing on non-existent memory region
get_mem_region() may return None for a non-existent memory region
so we need to check first before looking at its properties.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-01-21 22:08:59 -05:00
Daniel Leung 181d07321f coredump: add support for ARM Cortex-M
This adds the necessary bits in arch code, and Python scripts
to enable coredump support for ARM Cortex-M.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00
Daniel Leung 8fbb14ef50 coredump: add support for x86 and x86_64
This adds the necessary bits to enable coredump for x86
and x86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00
Daniel Leung 49206a86ff debug/coredump: add a primitive coredump mechanism
This adds a very primitive coredump mechanism under subsys/debug
where during fatal error, register and memory content can be
dumped to coredump backend. One such backend utilizing log
module for output is included. Once the coredump log is converted
to a binary file, it can be used with the ELF output file as
inputs to an overly simplified implementation of a GDB server.
This GDB server can be attached via the target remote command of
GDB and will be serving register and memory content. This allows
using GDB to examine stack and memory where the fatal error
occurred.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00