Try to catch issues related to platforms and HAL changes using this
basic sample. We have the same flag for a kernel test, but this is
skipped if no kernel changes are present in the PR, so we were missing
some coverage of platform related changes.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Thos tests/samples are used to build any PR onl all available boards to
verify basic sanity. Having the kernel tag means they can get excluded
for random non-kernel changes causing regressions. so remove kernel tag
to keep them in all CI runs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The seasonal overhaul of test identifiers aligning the terms being used
and creating a structure. This is hopefully the last time we do this,
plan is to document the identifiers and enforce syntax.
The end-goal is to be able to generate a testsuite description from the
existing tests and sync it frequently with the testsuite in Testrail.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Mostly build tests now, will be extended to verify CTF output once we
have this feature in sanitycheck.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In long mode, x86 does not support static IDTs or OpenOCD,
so disable the tests related to these features.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().
The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.
Limitations:
+ Right now the SDK lacks an x86_64 toolchain. The build will fall
back to a host toolchain if it finds no cross compiler defined,
which is tested to work on gcc 8.2.1 right now.
+ No x87/SSE/AVX usage is allowed. This is a stronger limitation than
other architectures where the instructions work from one thread even
if the context switch code doesn't support it. We are passing
-no-sse to prevent gcc from automatically generating SSE
instructions for non-floating-point purposes, which has the side
effect of changing the ABI. Future work to handle the FPU registers
will need to be combined with an "application" ABI distinct from the
kernel one (or just to require USERSPACE).
+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
of all memory. No MMU/USERSPACE support yet.
+ We are building with -mno-red-zone for stack size reasons, but this
is a valuable optimization. Enabling it requires automatic stack
switching, which requires a TSS, which means it has to happen after
MMU support.
+ The OS runs in 64 bit mode, but for compatibility reasons is
compiled to the 32 bit "X32" ABI. So while the full 64 bit
registers and instruction set are available, C pointers are 32 bits
long and Zephyr is constrained to run in the bottom 4G of memory.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This will prepare test cases and samples with metadata and information
that will be consumed by the sanitycheck script which will be changed to
parse YAML files instead of ini.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
