Commit graph

25 commits

Author SHA1 Message Date
Francois Ramu 715b246a2a include: reset bindings add the stm32h7rs serie
Add the support of the STM32H7RSX to the
include/zephyr/dt-bindings/reset/stm32h7_reset.h
which differs from the stm32h7 with an APB5 bus

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2024-06-06 00:41:43 -07:00
Declan Snyder 1db901e2c9 dts: bindings: Add bindings for NXP LPC resets
Add binding representing the peripheral reset controller
of the NXP LPC SYSCON heritage hardware including SYSCON
itself and the newer RSTCTL.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-05-21 16:49:42 -04:00
Jun Lin 011b730b4c driver: reset: npcx: add driver support for reset controller
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-04-16 09:09:13 +02:00
cyliang tw e22958ceaf soc: nuvoton: numaker: add support for m2l31x series
Add initial support for nuvoton numaker m2l31x SoC series
including basic init.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2024-03-11 14:22:55 +01:00
Girisha Dengi 6639756fae drivers: reset: Add reset controller for Intel Agilex5 platform
This is Intel's proprietary IP which controls individual module
reset signals. During each system driver initialization, these
reset signals will be used to bring module out of reset state.

Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
2023-07-25 16:58:01 +00:00
Erwan Gouriou 85aa3e1731 include: dt-bindings: reset: Add bindings for stm32WBA
Add reset bindings for STM32WBA SoCs.

Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
2023-07-11 15:05:05 +02:00
cyliang tw c448dceb57 drivers: reset: add support for NuMaker series reset
Add Nuvoton numaker series reset controller support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
Francois Ramu 806cfbf365 include: bindings: reset definition for the new stm32h5 serie
Defines the RCC reset registers for the stm32h5cx devices
Note that all stm32h5x do not have all the bus registers.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-03-28 15:07:51 +02:00
Benjamin Björnsson 17f96eba34 dt-bindings: reset: Add STM32C0 reset header
Add header to be included in STM32C0 series dtsi files.

Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
2023-03-14 17:35:37 +00:00
YuLong Yao bfe085070b dt-bindings: gd32: reset: add support for gd32a50x
add support for gd32a50x

Signed-off-by: YuLong Yao <feilongphone@gmail.com>
2023-01-12 21:45:38 +01:00
HaiLong Yang 2b72968d7f dts: arm: gigadevice: add gd32l23x series
Add initial support for gd32l23x series. gd32l23x used Cortex-M23, based
on ARMv8-M baseline, implement the System Timer.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2022-12-28 10:37:52 +01:00
Patryk Duda 31d3374627 dts: arm: st: mp1: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda b36f3bc412 dts: arm: st: wb/wl: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 0648e0e624 dts: arm: st: u5: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda a619f024a5 dts: arm: st: l1: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda df0c9f3cbb dts: arm: st: l0: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda c79cce57b3 dts: arm: st: g4/l4/l5: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 4310d29a46 dts: arm: st: g0: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 7dd9f11520 dts: arm: st: h7: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda e03aba03ec dts: arm: st: f2/f4/f7: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda 90b20f0e23 dts: arm: st: f0/f1/f3: Add reset controller node
Reset controller node is necessary to enable support for resetting
peripherials using RCC.

This patch also includes RCC reset registers offsets used by STM32_RESET
macro.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Patryk Duda d6f8e9ae5b drivers: reset: Introduce STM32 reset controller
This driver exposes STM32 RCC reset functionality through reset API.

Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
2022-12-09 09:43:36 -08:00
Dylan Hung 4224732a57 dts: bindings: reset: add binding for Aspeed AST10x0 reset
Add bindings for Aspeed AST10x0 reset driver.  The reset line can be
de-asserted or asserted through the syscon registers.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-12-05 14:36:16 +01:00
Gerard Marull-Paretas f7c13df36c include: dt-bindings: reset: gd32f3x0: fix ADDAPT1RST_OFFSET
The ADDAPB1RST_OFFSET was incorrectly set to 0xE0, but it is 0xFC in
this series.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-09-05 09:36:04 +00:00
Gerard Marull-Paretas 28b59890a6 drivers: reset: gd32: add initial support
Add a new reset driver for GD32 platforms. This driver controls the
reset registers from the RCU peripheral. It can be used to restore
peripherals to their initial state when initializing a device.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2022-08-29 10:30:49 +02:00