This commit adds flash controller instance for Ambiq Apollo3 Blue SOC
and Apollo3 Blue Plus SOC.
Also create the partitions on this flash controller node for apollo3_evb
and apollo3p_evb.
Signed-off-by: Aaron Ye <aye@ambiq.com>
If no HSFLL needs trimming, then `trim_hsfll()` should be compiled out.
This makes it easier to reuse the rest of `soc.c` out of tree.
Furthermore, some HSFLL instances can be trimmed before booting Zephyr,
so the FICR client properties in the DT binding should not be required.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The emulated GNSS driver behaves like a GNSS, implementing
device pm and the GNSS APIs, using only kernel features (
zephyr work queue and uptime) making it buildable on all
zephyr targets.
The purpose of this device driver is to tailor and validate
the gnss api test suite.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Add mfd_adp5585 and gpio_adp5585 driver. This driver enables ADP5585
as an GPIO expander.
This chip is used as an GPIO expander on i.MX93 EVK. GPIO pinctrl,
read/write and interrupt is supported.
Note that ADP5585 has 2 GPIO banks with 5 pins each. The driver combines
two group into a 16-bit port. Index 0~4 correspond to R0~R4 lines, index
8~12 correspond to C0~C4 lines. Index 5~7 is reserved unavailable.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
The counter driver needs to know what is the maximum
counting frequency of each timer peripheral.
Let's add it to its DT.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add binding for adi SDP-120 connector and header file
with marcos to map signals using signal names.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add driver for IS66WVQ8M4 PSRAM, using the MCUX FlexSPI interface to
write data to the PSRAM device.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Some instances of the FlexSPI IP support a different clock source being
used for port B of the FlexSPI instance. Add a devicetree property and
driver support to enable configuring this property of the hardware.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added EXMIF peripheral DTS description and bindings.
The peripheral operates as an SPI device.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
In the <board>.dts file, the definition for usart0 was found to be
redundant as the same information is already provided in the included
.dtsi file. this commit removes the duplicate definition of usart0,
resulting in a cleaner and more maintainable device tree configuration.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Add support for similar adin1100 phy, boath are 10Base-T1L,
only difference is that adin1100 connects through r/mii.
Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
Add mdio node for h5 and h7 series.
Since MDIO registers are part of the same ETH hw IP, keeping mdio
node just as a child of mac/eth, cannot see as appropriate to assign
an adddress to it.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
MDIO is part of the ETH IP, but some phy chip may need a
specific phy driver to set up certain vendor registers enabling
particular features.
Add support for stm32 mdio access.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Add Sequans GM02S modem binding using the sqn vendor prefix.
The modem has an active low reset signal.
Signed-off-by: Thibo Verheyde <thibo@dptechnics.com>
Intial driver adding intial script to receive only GGA, RMC and GSV
NMEA messages, configuring fix rate, setting enabled system and adding
power management with the module on-off pin.
Signed-off-by: Jeronimo Agullo <jeronimoagullo97@gmail.com>
Set RNG address to its non-secure alias.
See RM0493 STM32WBA5 Reference manual for details.
Using the secure alias (0x5..)instead of the non-secure alias (0x4..)
for this peripheral results in a SecureFault during kernel init if
TrustZone is activated, Zephyr is running as NSPE and RNG is
enabled.
Signed-off-by: Louis Feller <louis.feller@st.com>
Commit 246ea739bb ("dts/arm/st: wl: increase Sub-GHz SPI frequency to
12MHz") increased the Sub-GHz to 12 MHz. This matches the SX126x
datasheet, but there is no information about the maximum speed in the
STM32WL datasheet or reference.
This works fine when not using DMA. However with DMA activated (adding
entries to the device-tree and enabling CONFIG_SPI_STM32_DMA), I have
encountered some rare corruption. When it happens, the read from the
Sub-GHz device gets an extra 0x00 byte prepended, which confuses the
LoRaMac-node library and causes reception failures. Decreasing the
frequency to the next round number, that is 8 MHz (i.e. increasing the
prescaler from 4 to 6) fixes all the issues I encountered.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Spell checking tools do not recognize "iff", replace with "if and only if".
See https://en.wikipedia.org/wiki/If_and_only_if
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Convert the ht16k33 to use the input subsystem. This can still be used
with the kscan API with the zephyr,kscan-input driver, or use the
input-keymap one to generate input codes instead.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
1) Replace master/slave in API for new terms in eSPI spec 1.5
2) Reflect eSPI VW change and macro changes across eSPI drivers
3) Update terms in eSPI driver sample and eSPI test driver
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Update m2l31x.dtsi for adc support and update adc_numaker.c
to support acquisition time in 0~255 ADC ticks.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add basic functionality of Renesas SD/MMC driver. It can be used
for both gen3 and gen4 R-car boards, but tested only with H3ULCB,
Salvator XS M3 and Spider boards. This driver working with SDHC
subsystem.
The driver supports regularal reading/writing throught SD/MMC
controller buffer, DMA mode w/o interrupts and timing tuning.
Add gpio5 and sd0 nodes to h3ulcb and salvator xs which are needed
for working with SD cards. The GPIO node is needed for switching
voltage on SD card through gpio regulator driver.
Notes:
* the driver doesn't support SPI mode;
* SCC tuning and DMA mode based on IRQs are enabled by default;
* an address of a data buffer has to be aligned to 128 bytes if it
is not, driver will use non-DMA mode automatically;
* Renesas MMC DMAC doesn't support 64-bit DMA addresses, so for
case when we have 64-bit xref data address we use non-DMA mode;
* SD/MMC controller supports block size between 512 and 1 with
a lot of restrictions, more details you can find in code;
* support of HS400 mode isn't implemented inside driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit updates the device tree and memory header file
for the Intel MTPM 1.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace15_mtpm.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel LNL 2.0 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_ace20_lnl.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This commit updates the device tree and memory header file
for the Intel cAVS 2.5 platform to define the LSBPM and
HSBPM registers.
Changes include:
- Added node definitions for 'lsbpm' and 'hsbpm' in
intel_adsp_cavs25.dtsi and intel_adsp_cavs25_tgph.dtsi
- Updated adsp_memory.h
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
Add device driver for TI TMP114 I2C temperature sensor.
The driver only support basic functionality, i.e. fetch temperature
using default values.
Datasheet:
https://www.ti.com/lit/ds/symlink/tmp114.pdf
Signed-off-by: Fredrik Gihl <fgihl@hotmail.com>
For historical reasons, inversion mode is enabled by default in the
current implementation. This commit introduces an `inversion-off`
boolean DTS property, allowing it to be disabled if necessary.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
This commit implement the UART asynchronous API mode support.
When the API is used, the UART hardware cooperates with the DMA (MDMA)
module to handle the the data transfer and receiving.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Adds support for the PGOOD pin. This pin is asserted by the
regulator when converter startup has completed and the output
is stable. If the PGOOD pin is not used, the PGOOD state is
check via the PGOOD_PIN_STS bit.
Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
Deprecate the use of location_* properties in the i2c_gecko driver
and migrate to the pinctrl api for enhanced maintainability and
compliance with current standards.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@capgemini.com>
Enable serial communication through UART port between HDMI ports.
Signed-off-by: Myeonghyeon Park <myeonghyeon@tsnlab.com>
Signed-off-by: Junho Lee <junho@tsnlab.com>
This property will allow PWM driver allocate data buffer
in appropriate memory region.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
This enabled extended sleep for Renesas SmartBond(tm).
Extended sleep is low power mode where ARM core is powered off and can
be woken up by PDC. This is default sleep mode when CONFIG_PM is
enabled.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Squash the two copies of this file found in `dts/arm` and `dts/arm64`.
Their contents were identical up to devicetree property ordering.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This file was moved to the `dts/arm64` directory 3 years ago:
3539c2fbb3
However, the original file in `dts/arm` was left by mistake. Since then,
it's been unused and seldom updated, but it hasn't diverged much.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Driver already handles the case when 'reset-gpios' is not provided, so
remove 'required: true' from bindings to allow boards / shields definition
without reset signal being connected to any Zephyr controlled GPIO.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit refactors the Intel SSP DAI driver to support dynamic
management of SSP IP. This change additionally separates the management
of the DAI part from the management part of the SSP IP.
Key changes:
- Add new static functions to manage SSP IP power.
- Update the DAI SSP configuration functions to use the new management
approach.
- Update device tree bindings and instances to reflect the new SSP IP
management mechanism.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
This file is basically a copy of the AM62x M4 dtsi but an
additional mcu_uart1 interface.
The internal clock frequency feeded into the UART IP is
96 MHz instead of 48 MHz, which is different to the AM62x.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
We define two frequencies in the am62x_m4.dtsi file.
Use DT_FREQ_M for both frequency to make them more
human-readable and easier to understand.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The commit restricts erase-value to either 0xff or 0x00.
On program-erase type devices writes can only change from
erase value of bit to opposite, ease usually consists of two
operations which is programming the opposite value to every bit
of erase range and then turning back all bits to the "erase-value";
above makes it impossible to have erase value of device to be other
than 0xff or 0x00.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
This implements basic driver to utilize the I3C IP block
on NPCX.
1. I3C mode: Main controller mode only.
2. Transfer: Support SDR only.
3. IBI: Support Hot-Join, IBI(MDB).
Controller request is not supported.
4. Support 3 I3C modules:
I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Chip it82xx2 series change the HW sha module and it82xx2 series
can't use original sha driver anymore, so move sha0 node from
it8xxx2 to it81xx2 series.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Updated dts for MCXN94x with support for CTimer.
Signed-off-by: William Tang <william.tang@nxp.com>
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
add gpio_intel driver with acpi based resource enumeration support.
Also updated test cases overlay with new dts entires.
Signed-off-by: Najumon B.A <najumon.ba@intel.com>
The ace20 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The ace15 description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The tgph description has incorrect number of SSP instances
described. Correct number should be 3.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
FTM internal counter can be clocked by one of three clock sources
independent of the module bus clock. This patch introduces a DT property
to perform the clock selection from DT.
DT sources are updated to keep the current clock selection for all boards,
with exception of ucans32k1sic board which is migrated to use system
clock by default, as this seems to be a better choice for most cases.
Some PWM LED samples require slower clock so overlays are added for
those cases.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Set RTC clock source to the internal 32 KHz LPO. Currently RTC clock is
used to source RTC counter and FTM counter.
Fixes#71289
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for half-duplex (3-wire) SPI operation using the Raspberry
Pi Pico PIO. To allow control of the size of the driver, including
half-duplex support is optional, under the control of Kconfig options.
The original PIO source code is also included as a reference.
Corrected 3-wire tx/rx counts.
Enable half-duplex code based on DTS configuration
Replace runtime checks with static BUILD_ASSERT()
Remove too-fussy Kconfig options
Removed PIO source per review request
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.
Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.
Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The MAC address macros are ridiculous in this driver.
Rewrite to be simpler and use eth.h common function.
Also, clarify the mac address generation on the DT overlays.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Adds a DAC driver for Texas Instruments DACx0501 family of devices
Signed-off-by: Eran Gal <erang@google.com>
Co-authored-by: Martin Jäger <17674105+martinjaeger@users.noreply.github.com>
Add a VEVIF node to be used for communicating with SysCtrl (cpusys).
This is the only part of the SysCtrl VPR exposed to local domains.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Enable MIPI mode to be set via devicetree, for displays that support
multiple MIPI DBI modes. This commit also adds new helpers for displays
that allow drivers to initialize the entire MIPI DBI configuration
structure from devicetree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates the SRAM configuration in the STM32L475 device tree:
- `sram0` size reduced from 128K to 96K.
- `sram1` added with 32K.
These changes correct memory settings to prevent initialization failures.
Signed-off-by: Tianshuang Ke <qinyun575@gmail.com>
Nuvoton NPCX chips have reset registers which allow to reset the
peripheral hardware modules. This commit adds the support by
implementing the reset driver. Note that only the reset_line_toggle API
is supported because of the nature of the reset controller's design.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
If I2C3 switches from GPH1/GPH2 to GPB2/GPB5, extend setting
is required.
Test: Accessing I2C is normal if I2C2, I2C3, I2C5 are switched.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Copy the DMA channel information to both UART and SPI
instances of the Flexcomm as only one of them can be
active.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Enable serial interface on i.MX8ULP.
This also includes a SHA update for hal_nxp which
pulls in the following commits relevant to Zephyr:
* 3366f234ed47 build: hal_nxp: add TPM counter support
* 6544455fcf46 Compile in PXP driver if LVGL is set to use
PXP.
* 31463a848bcd devices: MIMX8UD7: add definition for
LPUART_RX_TX_IRQS
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Currently, all devices are initialized at boot time (following their
level and priority order). This patch introduces deferred
initialization: by setting the property `zephyr,deferred-init` on a
device on the devicetree, Zephyr will not initialized the device.
To initialize such devices, one has to call `device_init()`.
Deferred initialization is done by grouping all deferred devices on a
different ELF section. In this way, there's no need to consume more
memory to keep track of deferred devices. When `device_init()` is
called, Zephyr will scan the deferred devices section and call the
initialization function for the matching device. As this scanning is
done only during deferred device initialization, its cost should be
bearable.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
CSS was deprecated from the mcu-sdk. Removing driver from lpc55s36
to clear build error.
This is a temporary patch to remove the build error.
Fixes#69961
Signed-off-by: David Leach <david.leach@nxp.com>
Configure the 'soft-off' power state for manual selection only in the
DTS for Intel ADSP ACE 1.5 MTPM and ACE 2.0 LNL platforms.
Changes include:
- Setting 'min-residency-us' to 0 to indicate that the 'soft-off' state
is not intended for automatic selection by the power management
policy.
- Adding a 'status' property set to "disabled" to prevent the power
management policy from using this state during its decision process.
The 'soft-off' state remains available for manual selection by calling
`pm_state_force`. This change ensures that the state can still be used
when explicitly requested by the system or application, providing
flexibility for power management operations.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Implement a sensor for the output diagnostics of the power train
switch TLE9104.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This commit enables pinctrl on i.MX8ULP. This includes:
1) Adding `pinctrl_soc.h` header file.
2) Adding DTS node for IOMUXC1, which is one of the
IPs responsible for managing the 8ULP pads.
3) Adding .dtsi with pin definitions. For now, only
the LPUART7 pads are added to this file because this
is going to be the only consummer for now.
4) Modifying the `pinctrl_imx.c` driver to work for 8ULP.
5) Enabling the `CONFIG_HAS_MCUX_IOMUXC`, which is a
dependency of `CONFIG_PINCTRL_IMX`.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add definitions of PWM peripheral instances so it can be utilized
on nRF54H20 and nRF54L15 devices.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add binding for sitronix ST7796s, a MIPI DBI display controller
supporting up to 320x480 displays at 18 BPP
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The SparkFun Pro Micro header pins are numbered D1, D0, GND, ... from top
left whereas the SparkFun Pro Micro RP2040 and the Adafruit KB2040 boards
are using gpio 0, 1, GND, ... , so the pro_micro: connector gpio-map of
these boards should reflect that.
Graphical Datasheet for SparkFun Pro Micro RP2040:
https://cdn.sparkfun.com/assets/e/2/7/6/b/ProMicroRP2040_Graphical_Datasheet.pdf
Graphical Datasheet for SparkFun Pro Micro:
https://cdn.sparkfun.com/assets/f/d/8/0/d/ProMicro16MHzv2.pdf
Pinout of the Adafruit KB2040:
https://learn.adafruit.com/assets/106984
Please note that the KB2040 uses CircuitPython pin labels D0, D1 which does
not seemt correspond to the Arduino labels D0 and D1 used by the Pro Micro.
Signed-off-by: Daniel Irekvist <ulmanyar@gmail.com>
Add devicetree binding for NXP LCDIC. This controller is capable of
driving displays in 8080 or SPI 3/4 wire mode, and optionally swapping
endianness of display data as it sends it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add EDMA channels for LPUART RX and TX to LPFLEXCOMM 2 and 4, as these
nodes are enabled with the UART driver
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The initial version of an input driver for Cirque Pinnacle ASIC supports:
* Setting sensitivity
* Choosing between relative and absolute modes
* Relative mode
* Primary tap
* Swapping X and Y
* Absolute mode
* Setting number of idle packets
* Clipping coordinates outside of active range
* Scaling coordinates
* Inverting X and Y coordinates
Signed-off-by: Ilia Kharin <akscram@gmail.com>
For now DSI settings are hard-coded for the specific
LCD module used on the STM32H747I Discovery board
Signed-off-by: Erik Andersson <erian747@gmail.com>
To support the NT35510 display, some additional
options needs to be configurable in the STM32
DSI peripheral
Signed-off-by: Erik Andersson <erian747@gmail.com>
Add support for performing pinctrl operations. For now,
the only supported operation is applying the pinctrl default
state. Pinctrl is left optional to allow for scenarios in which
this is not required (e.g: AMP system in which another
OS configures the pinctrl).
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add a property to select the push-pull GPIO output type to drive the
I2C recovery. The default is open-drain.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enable clock control for i.MX8ULP. This consists of:
1) Adding a PCC node in the DTS
2) Adding a header file containing the definitions
of the clocks used by the peripherals to be enabled.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Enable sleep mode on LPC55S69 (corresponding to zephyr's runtime idle
mode). Add DT description and power api implementations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Rename ad5592 files in dts, driver and include to ad559x and add support
for I2C bus which is required for AD5593.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Based on the iis2dlpc driver, with some significant differences in
interrupt handling.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Add common gpio node to pinctrl node (interrupts are shared between ports)
and syscon for interrupt edge detection register in order to support
interrupts in rzt2m gpio
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Add irqs to rzt2m gpio bindings in order to add interrupt support to rzt2m
gpio driver and adds common gpio node to store interrupt config (irqs are
shared between ports)
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Remove the unused "tx-delay-comp-offset" property from the base CAN FD
controller devicetree binding.
Having a static Transmitter Delay Compensation (TDC) offset is useless.
The offset needs to match the data phase timing parameters in order to
properly configure the second sample point when transmitting CAN FD frames
with BRS enabled.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove ethernet-fixed-link binding as it is redundant with the
phy bindings. Clearly, ethernet does not work without the L1
layer, which is a phy device, or an integrated mac/phy device,
and all of these things should be described properly in DT.
The schema did not even come with a compatible, meaning nodelabels
were hardcoded into the drivers, which is unacceptable.
- Remove the binding file for ethernet-fixed-link.yaml.
- Remove fixed link functionality from the nxp s32 gmac driver.
Since this functionality is already covered by the phy support,
it is redundant.
- Remove fixed link include from the s32 gmac binding.
- Remove fixed link include from the nuvoton numaker binding.
As far as I can tell the corresonding driver does not even
use it anyways, and I did not find any board with this device
that describes a "fixed link".
- Move the definition into the nxp,kinetis-ethernet binding
as the eth_mcux driver, which is already being deprecated,
does use this, contain the debt to the legacy driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Added configuration of long press reset functionality.
Includes ship/hibernate to wake debounce time and
disabled/one_button/two_button mode selection.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
The DHT20 sensor is a temperature and humidity sensor that uses I2C to
communicate with a microcontroller. The DHT20 sensor is Aosong.
use standard crc
update description to add reference to AHT20 and AM2301B
clean code, use defines and bit manipulation
add dht20 to i2c test suite for build tests
update bit manipulation
use more defines instead of raw numbers
add bindings to allow aht20 or am2301b to be used in devicetree
in all 3 cases, the same dht20.c driver is compiled
Signed-off-by: Nathan Olff <nathan@kickmaker.net>
1. Update EDMA driver for version 4
2. The DMAMux module is not always present. Use the
feature define to make this optional.
3. Use the EDMA_SetChannelMux API for SoC's that supports
this feature.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add enum for `constant-charge-voltage-max-microvolt` property to
signalize improper values given with device tree at compile time.
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
Maximum charging current is selected with an external resistor in
the MAX20335 charger. Therefore it is not possible to configure it
with software directly. There is only a capability to limit current
set with hardware but configuration of the limiter is not
straight-forward.
To reflect real functionality, drop usage of
`constant-charge-current-max-microamp` property as an required one and
use custom `chgin-to-sys-current-limit-microamp` instead.
Use enum in binding file to signalize improper values at compile time.
Drop support for `CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA` API property
since this cannot be handled.
The `max20335_get_constant_charge_current()` function become useless so
remove it.
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
Rework the data scaling algorithm for the "deadzone" mode so that the
deadzone is subtracted from the input rather than from the output. This
makes the whole output range usable rather than making the output jump
from the center value to the minimum deadzone range.
This changes the calibration data structure as well so now all values
refer to the input data, which is more coherent.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Byte value written to the device's
ERXFCON: ETHERNET RECEIVE FILTER CONTROL REGISTER
Sets the devices receive packet filter, optional. If not set
in device tree previous hard coded value`0xA3` is used.
Uni, multi and broadcast packets with valid CRC are accepted.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
This will update host dma copy aligmnet as with current
high value in some cases it was not possible to fully
empty the buffer
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
MODEM_UBX: Adds Support for UBX Messages in Modem Subsystem.
GNSS API Supported: get_supported_systems, set_fix_rate, get_fix_rate,
set_enabled_systems, get_enabled_systems, set_navigation_mode,
get_navigation_mode.
Boards Tested: MIMXRT1062_FMURT6, VMU_RT1170.
Note: Partial support for U-BLOX Messages is provided as of now.
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Signed-off-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
The STTS22H is an ultralow-power, high-accuracy, digital temperature
sensor offering high performance over the entire operating temperature
range. This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/resource/en/datasheet/stts22h.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add ability to set a wakeup counter in case OS Timer is
disabled in certain low power modes. Also add code to
compensate the tick value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Enables usage Bluetooth LE GATT as a serial endpoint to exchange data
using UART APIs. This implementation is compatible with UART Interrupt
Driven APIs and uses the nus-uart device-tree node properties to
configure FIFO buffers for transmitting and receiving. Defining
multiple instances of the driver is possible and it allows implementing
multiple GATT NUS service instances to exchange data as separate serial
endpoints.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
"RW pinctrl" is clearly SOC specific naming for an IP
that is not necessarily constrained to live on one SOC series.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There were missing global dppic and ipct channels configuration
that allows to deliver events from global peripherlas like GRTC
to Radio domain.
Add missing configuration to nrf54h20 dtsi file.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The GRTC channels and irqs configuration for Radio domain
is SOC specific not board specific. Move the configuration
to SOC dtsi file.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
The child-owned-channels property of GRTC is used by nrfx_grtc
driver to exclude channels for common pool of channels allowed
for dynamic allocation. That is sort-of workaround for missing
property that allowes to remove some channels from the pool.
There are also not aligned GRTC IRQs for nRF54H20 and nRF54L15.
Only one of avaialbe IRQs was added to GRTC in DTS whereas
there should be two. That allows to find second IRQ by other
drivers that use GRTC peripehral.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
Split up the driver for the PWM controller MAX31790
into a multi function device driver.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the Audio Link Hub (ALH) nodes from the ACE 2.0 LNL DTS file.
This patch cleans up the Device Tree Source by removing the individual
ALH stream/FIFO nodes. The ALH hardware is not present in the ACE 2.0
architecture, and these nodes are therefore not applicable.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain definitions for the Intel ADSP ACE
2.0 LNL (Lunarlake) platform in the Device Tree Source (DTS).
Changes include:
- Removing the definitions for io2_domain, io3_domain, and ml1_domain,
which are no longer present in the ACE 2.0 LNL configuration.
- Renaming and reassigning bit positions to existing power domains to
reflect the updated power management architecture.
The reordering ensures that the DTS reflects the current power domain
architecture of the ACE 2.0 LNL platform, facilitating accurate power
management within the SoC.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Changing the power domain from 'hst_domain' to 'io0_domain' for the HDA
DMA link in/out nodes. This aligns the power domain assignments with the
actual hardware configuration and ensures that the power management
subsystem can accurately manage the power states of these interfaces.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch reorders the power domain node definitions in the ACE 1.5
Meteorlake DTS file to improve readability and facilitate comparison with
the documentation.
Changes include:
- Reordering power domain nodes by their bit positions.
- No changes to the bit positions themselves; they remain as originally
defined.
This reordering does not affect the functionality but makes the DTS file
more maintainable and easier to cross-reference with the hardware
specification.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Some SAI instances are mutliline, meaning they can have multiple
TX/RX data lines (channels). Depending on the board, the index
of the TX/RX data lines that are connected to the consumer
(e.g: the codec) may not always be 0. This commit fixes this
issue by adding support for passing the index of the used
TX/RX data lines through the DTS.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add definition of the nRF54H20 SoC with its Application, Radio,
and Peripheral Processor (PPR) cores and an initial set of
peripherals.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove all optional, initial CAN sample point properties and rely on the
CAN timing calculations to automatically pick the preferred sample point
location based on the initial bitrate.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Make the properties for setting the initial sample points for both the
classic/arbitration phase and the data phase optional.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Implement a sensor for the output diagnostics of the low side
switch BD8LB600FS.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Split up the driver for the low side switch BD8LB600FS into a GPIO
and MFD part.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This binding is for the NXP FlexComm Interface. The
driver will setup an interface for use as a UART, SPI
or I2C device.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
These list of files add basic support for StarFive
JH7110 SOC Device Tree includes for VisionFive2
board.
Signed-off-by: Pratik Farkase <pratik.farkase@wsisweden.com>
Split the common keyboard scanning code out of the XEC specific driver
and use the generic code instead.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Convert the XEC keyboard scanning driver from kscan to input, add the
corresponding kscan compatibility node to the current board, build test
only.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This is a follow-up to commit 4db40601dd.
There are two ECB instances in nRF54H20 and the above commit added
only one of them.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
And add the corresponding bindings.
Move alse the already existing bindings for nrf-dppic, nrf-ppi,
and nrf-ipc so they are located together with the new ones and
in more appropriate folders (DPPIC and PPI peripherals are not
related to ARM, and IPC is for sending and receiving events,
not messages, so ipm/ does not seem to be the best fit for it).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Enabling peripherals at SoC dts files should not be done, unless there
are good reasons (e.g. always needed peripherals). NFCT node should
either be enabled at board level, or, at application level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Some CAN transceivers have a lower limit on their supported bitrate. Add an
optional "min-bitrate" for specifying this limit via devicetree.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The pit had a few warnings about
the format of the register address
being uppser case and one of the
reg index values were incorrect.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add new devicetree bindings for F4 and L1 series for configuration of
block size used in flash write operations.
Allow byte-size write operations in `flash_stm32f1x.c`. This file is
being shared between F0, F1, F3, L0 and L1 series. L0 and L1 series
allows for single byte writes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
This commit enables the IRQSTEER interrupt controller
on NXP's XTENSA-based i.MX8QM and i.MX8QXP.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Define the MPU attribute to be ATTR_MPU_EXTMEM for the
external region (qspi- or octo-spi NOR flash)
starting at 0x90000000 of the stm32h7 serie.
A XiP region should be Included inside with attribute
ATTR_MPU_IO, to access the external memory in XIP.
The stm32h7a/h7b serie as another external area at 0x70000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add Nuvoton numaker series flash memory controller(RMC) with erase,
read & write features of soc-flash.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add Open Alliance spi protocol support.
Open Alliance is a chunk-based SPI protocol, based on sending
over SPI an ethernet frame divided in smaller chunks, using a
specific 32-bit header for each chunk transferred. All chunks
can be sent or received by a single dma transfer.
Default mode is set to Open Alliance SPI without protection,
since the adin2111 dev. board comes shipped this way.
Tested:
- Open Alliance SPI, no protection (default board shipped)
- Open Alliance SPI, protection
- Generic SPI, no crc
- Generic SPI, with crc8
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
Define a single node that reflects the LCDC IP. Instead of defining
the same IP block twice with different compatibles (mipi dbi, display)
we define a single node for the default display interface and
other interfaces like the MIPI DBI should override the compatible entry
with the appropriate one within its DTS overlay file.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Exhibit Renesas LCD controller's driver implementation. The driver
is intended to employ the controller in the continuous mode so
it can drive display panels in the parallel RGB mode.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
The MRAM has no concept of erase blocks or pages, so this is treated as
driver configuration.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Enabled the PIT and Multi channel support
for some of the rtXXXX devices.
- rt1010
- rt1060
- rt1160
- rt1170
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Updating the nxp,pit driver to support mutliple
channels. Updating the dts and board overlays
to account for the changes.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add a new binding that should help with samples or MBOX tests by getting
information from DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
For sharing pin definition property with `worldsemi,ws2812-gpio`,
rename `output-pin` to `gpios`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
ws2812-gpio's `in-gpios` property is not used as an input pin.
Renaming it to `gpios` to reflect the actual situation.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
By default N_VBUSEN signal is used by the host to define if VBUS
signal should be used for power supply (VBUS-IPSOUT).
This feature enables the possbibility to change this behaviour.
When N_VBUSEN detection is disabled, axp192 will automatically
decide to use VBUS (REG10H[7] = 1).
Please refer to datasheet for details.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
AXP192 features an EXTEN pin that is on output only.
This commit appends control of EXTEN pin to gpio functionality
of AXP192.
Port-Mapping is as follows:
- [0..4]: GPIO0..4
- [5]: EXTEN
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
This adds the minimal get_time/set_time support for the rp2040 and
enables support by default on the Pico boards. This doesn't support
configuring the clock source or alarm interrupts yet.
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
Utilization of chip interrupt line is mandatory to assure proper
charger state control. Handle interrupt to prepare the driver for
implementation of such functionality.
Modify charger status update so the current state is fetched in the
interrupt handler.
Use level based interrupts combined with interrupt disabling for a
period of time after interrupt handling to reduce number of interrupts
triggered by the charger. There may be a case where the charger
produces burst of interrupts for a several seconds and if the code
attempts to handle every single interrupt separatery then the system
might be significantly overloaded.
Co-authored-by: Bartosz Bilas <b.bilas@grinn-global.com>
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
Add new bindings to describe the BELLBOARD peripheral in its two
_programming modes_ local or remote.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new nodes for PPR's VEVIF. In app cores, VEVIF registers are part
of the VPR peripheral, so it is exposed as a child node (since it
requires its own properties, eg #mbox-cells). In VPR, it's a CPU child
since it's not a memory-mapped peripheral, but used with CSRs.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
To allow EDMA configuration with the help of the DT_INST_DMAS_*
and DT_DMAS_* macros, all that a consumer node needs to know
is which channel to configure and what MUX value needs to be
used. As such, this commit allows doing this by forcing the
dma-cells property to 2, each cell representing one of the
aforementioned properties.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
To enable per peripheral queue pool sizing options add some bindings to
the i2c controller to setup sq/cq pool sizing.
Its possible this could go away with a shared application pair of pools.
The shared pool would require some added function pointers though to
deal with the variants as the shared pools would need a lock.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Added is_enabled devicetree property to fake regulator.
Allows testing of init behaviour when regulator is enabled
in hardware.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
On HAL RTD version 1.0.0, there is available Canexcel_Ip_DeactivateMD()
API that have similar capabilities as can_nxp_s32_abort_msg() API,
can use to instead.
Remove the reg grp_ctrl and reg base_dsc_ctrl that unused
after implementation this.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Do not enable Standby low-power mode by default since the associated
Kconfig PM_S2RAM is disabled by default. Otherwise we could enter an
unsupported low-power state.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add devicetree based settings for resolution, axis inversion and sleep
mode enable. Keep the resolution setting in its own function so it can
be called by the application again in runtime if needed.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The nRF91 series devices, when running the Serial LTE Modem (SLM)
application starting with nRF Connect SDK 2.6.0, can now be used as
standalone modems via the generic modem_cellular driver.
A configuration to run the cellular_modem sample on the nRF9160 DK
(plugged in to another nRF91 series device running SLM) is provided.
Signed-off-by: Tomi Fontanilles <tomi.fontanilles@nordicsemi.no>
Add memory-region to nordic,nrf-spis binding. This commit aligns SPIS
shim to utilize memory-region property. This optional property enables
user to specify placement of dma buffers in memory region. It is done
by assigning to memory-region property, phandle to node with
zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given device, buffer
is placed in default RAM region with other data.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add an initial input driver for the PixArt PAT9125EL, just core
functionalities for now, will add more configuration properties at a
later stage.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This adds additional memory region property
to NFCT peripheral. This is not mandatory
property, it adds possibility to user to
specify memory region for DMA transfer.
If it is not set then data buffer is placed
in default RAM with other data.
Signed-off-by: Kamil Gawor <Kamil.Gawor@nordicsemi.no>
Signed-off-by: Dominik Chat <dominik.chat@nordicsemi.no>
This is a setting that depends on the board or application, so it should
not be part of SoC definition files.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit introduces a driver for ADC keys, a common circuit design where
keys are connected to an ADC input via a resistor ladder.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Added a simple driver for RRAM. It is implemented as a flash driver,
because the "RRAM eFlash" macro obeys flash-like constraints.
Although users are not required to erase before write.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add driver for ScioSense ENS160 multi-gas sensor. The driver includes
support for I2C and SPI, attributes for setting temperature and
humidity compensation and data ready trigger.
Also add ScioSense to the list of vendor prefixes.
Signed-off-by: Gustavo Silva <gustavograzs@gmail.com>
Add clarifications to mipi-dbi bindings to avoid the confusion
between two options, write-only and duplex.
Signed-off-by: Eve Redero <eve.redero@gmail.com>
Change reset pin polarity for MIPI DBI SPI controller, so that the board
devicetree is responsible for setting the GPIO to active low, and the
driver always sets the pin to a logic 1 to reset the display.
Fixes#68562
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Unlike SPI nodes, I2C nodes (i2c20, i2c21, i2c22 and i2c30) did not have
this required property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove pinctrl from device tree since it is not required
when internal oscillator is used.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Add FlexSPI clock source to RT1010 devicetree definition for FlexSPI
node, to match FlexSPI clock source defined on standard FlexSPI dt node
that is removed in the RT1010 devicetree.
Fixes#68488
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
... so that there is no need to include that header individually
for every added board based on an nRF SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add definition of the nRF54H20 SoC revision EngA with its Application,
Radio, and Peripheral Processor (PPR) cores and basic peripherals:
GRTC, GPIOs, GPIOTE, and UARTs.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a set of bindings that will be used in the nRF54H20 SoC definition.
Extend the existing GPIOTE binding with properties needed for this SoC.
Also do a tiny clean-up in the bindings added recently for nRF54L15
(HFXO and LFXO).
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
