Filip Kokosinski
28c7674c66
dts/riscv: add riscv compatible string where it's missing
...
This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
Gerard Marull-Paretas
6edb0624d8
soc: riscv: gd32vf103: simplify MCAUSE exception mask handling
...
The exception mask needs to cover MCAUSE bits 11:0, there's no need to
overengineer this setting using DT properties.
Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-15 09:58:03 +01:00
Gerard Marull-Paretas
0f73e8fd3e
dts: arm/riscv: gigadevice: s/gigadevice/gd
...
To stay consistent with other vendors, use vendor prefix (gd).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-10 20:59:21 -05:00
