The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.
Also make it the same type as `config_delay_us` (`uint16_t`).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
