Commit graph

119 commits

Author SHA1 Message Date
Kumar Gala 9ed4f39110 dts: microchip,xec-timer: Add properties for GIRQ info
Add girq and girq-bit to encode per device information.  This allows the
driver to get any device unique info from device tree.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-11 07:59:38 -06:00
Jose Alberto Meza da87abd971 dts: arm: microchip: Adjust DT IRQ priorities
Adjust default IRQ priorities.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2020-01-28 20:13:36 +02:00
Daniel Leung 6ecb36cbe0 dts: arm: mec1501hsz: rename I2C nodes
The I2C controllers on the MEC1501 SoC can be attached to
different I2C output line. For example, the I2C #0 controller
can be used with I2C7 physical lines out of SoC. The output
selection is done by the attribute "port_sel". This renames
the parent I2C nodes on the SoC side to refer to
the controller themselves instead of the output lines to
avoid confusion. The labels of these nodes are also renamed
to reflect the controllers.

On the board level, the DTS labels are overwritten to indicate
the actual output lines.

Aliases are also provided in both SoC and board levels to
provide shortcuts to the DTS nodes.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-01-18 13:33:20 -05:00
Scott Worley c8b1eb79a1 drivers : spi : mec1501 : XEC SPI driver
SPI driver for MEC1501 QMSPI supporting synchronous only.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-10-23 19:18:32 -07:00
Francisco Munoz 8a12d40a72 dts: bindings: kscan: Add dts entries and bindings for kscan
Indtroduction of generic device tree bindings for keyboard scan devices.
In addition, device tree node entries and dt specific bindings where
also implemented for Microchip MEC1501

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-10-16 13:29:21 -07:00
Tomasz Bursztyka bce525fdcf dts/arm: Add support for the ADC in MEC1501hsz
It has one instance.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-09-25 06:12:52 -04:00
Jose Alberto Meza ac16bf7f4c dts: espi: Cleanup eSPI block device tree
Move MCHP-defined NVIC interrupts to interrupts field.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2019-09-20 14:30:40 -04:00
Tomasz Bursztyka bea2714cae dts/arm: Add the 9 MEC1501 PWM instances.
All disabled by default.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-19 20:45:37 -04:00
Francisco Munoz 34f4e30615 dts: arm: microchip: Add dtsi entries for PS/2 devices in MEC1501
Create new nodes for PS/2 devices which can be used for
mouse and keyboard

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-09-18 13:23:52 +08:00
Tomasz Bursztyka 5a09a51e31 dts/arm: Add the 3 MEC1501 basic timer instances.
4 are found: 2 with a counter of 16bits and 2 with a counter of 32 bits.
However, first 32bits instance will not be exposed as it will be used by
rtos timer driver directly to implement k_busy_wait()

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-14 12:13:49 +08:00
Tomasz Bursztyka e83f4fad29 dts/arm: Add support for the watchdog in MEC1501hsz
It has one instance of this watchdog.

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2019-09-07 09:56:58 -04:00
Jose Alberto Meza 1810d10386 dts: espi: mchp: Add dts bindings for XEC eSPI driver
Add device for eSPI driver for MEC family

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2019-07-25 08:23:38 -07:00
Scott Worley bdaab8cfa0 drivers : timer : Add MEC1501 32KHz kernel timer driver
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-07-24 14:58:41 -07:00
Kumar Gala 3c8f8cb256 dts/arm/microchip: Mark uart & i2c nodes as disabled by default
Have the SoC dtsi files for microchip mark the devices (uart & i2c) as
disabled by default and let the board dts files enable which one's they
need/use (which is what's happening already).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-20 17:21:01 -04:00
Kumar Gala 0bed1007ed dts: cleanup missing #{address,size}-cells
A few i2c and spi bus nodes were missing #address-cells and #size-cells
properties.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-06-20 22:48:57 -05:00
Francisco Munoz 2452b84c89 dts : Introduce gpio node entries for Microchip MEC
Dts Nodes for all the GPIO portswere defined. In addition,
a new binding file was created for the gpio driver.

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-05-08 16:39:54 -07:00
Jose Alberto Meza 291e1289a0 dts: mchp: Add Microchip I2C SoC device tree
Expose MEC1501 5 I2C/SMB  controllers
Add Microchip specific I2C device tree properties

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2019-05-08 15:02:26 -07:00
Scott Worley a0a9a1f905 dts : arm : Add Microchip MEC1501 SoC device tree
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupts are configured in
direct mode.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2019-04-30 14:08:23 -07:00
Francisco Munoz f416327827 arch: arm: Add Microchip MEC1701 SoC
Initial support for Microchip MEC1701 series is incorporated to the
tree. Additional support for UART is also included. This SOC supports
two operation modes for interrupts (Direct and Aggregated). For this
commit, the interrupts are configured in direct mode.

Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-08 21:38:54 -05:00