MEC172X series SoCs share most IP but the -LJ series expands the PWM and
ADC channels available as well as defines extra pinctrl pins.
Separating these better to be able to simplify their inclusion and
driver code. Any board based on either the -SZ or -LJ package can just
include the mec172x<sz/lj> dtsi files for their specific package.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move the two UART nodes so that they are under "soc" rather than "espi",
leave only xec-espi-host-dev nodes there.
The UART device can be used indepdently by the driver uart_mchp_xec.c
and it's normally initialized before before the espi one.
Moving the device node up a level so this does not trigger a false
positive on the build time priority checking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Deleted adc_mchp_xec.c and microchip,xec-adc.yaml file.
DTSI, yaml, CMakeLists.txt and Kconfig.xec files are
updated for compatible.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and
MEC15xx SOC.
ADC smapling clock configuration updated using DTS.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Microchip XEC devices specify GPIO pin using octal numbering and
organize pins in banks of 32. Chip documentation does not use
bank naming rather naming each pin by its octal number. This has
led to the developer having to calculate the bit position of a pin
in its 32-bit bank when a specifying the pin for GPIO usage. We
created a set of defines for all possible GPIO pins that specify
the DT GPIO bank name used in the chip level DTSI files and the
bit position in that bank.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Set default interrupt priority to 3 for all Microchip MEC172x eSPI
host child devices except the UART's which are set to 1.
The espi peripherals don't require the maximum priority hence they
are being made uniform and a lower priority 3.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add MEC172x full duplex qmspi driver version to support full
duplex transfers as expected by the Zephyr spi driver model.
On every spi clock we transmit one bit and receive one bit.
This driver will work with Zephyr SPI NOR driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
updated dts variables naming (hyphen instead of underscore).
moved all properties in microchip ldma yaml to a separate include file,
these properties will be common with the (to be added)
full duplex spi driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Use consistent name for SPI HW block properties across Microchip
HW, so applications using a device tree overlay work
transparently.
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
In order to bring consistency in-tree, migrate all dts code to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The binding did not define the PWM cells. Only channel and period have
been added as they are the minimum required ones (flags are not supported).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update Microchip XEC TACH driver to support MEC172x.
Standardize device tree properties between chips.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for MEC172x series to Microchip XEC PWM driver.
Standardize device tree properties for both SoC families.
Standardize device structure usage.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Since we are moving to pinctrl, removing pinmux.c
from mec172x board folder and removing pinmux from dts
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add driver for MEC172x QMSPI with local DMA(LDMA). The driver
support SPI asynchronous operation.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
MEC172x eSPI driver, eSPI pin programming, interrupt updates related
to eSPI and other updates for MEC172x eSPI driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add ADC driver version 2 for MEC172x using new in-tree headers
and device tree properties. Update the ADC shell for the new driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC has been using the standard NS16550 driver.
Using the standard NS16550 driver requires extra HW programming
for XEC UART in board level and did not support XEC GIRQ interrupt
programming. We add an XEC specific driver and remove UART specific
register programming from the board level and implement interrupt
support. Also, by implementing a SoC specific driver we can add
driver PM in the future.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Microchip XEC two custom DT properies girqs and pcrs cell sizes
are defined as constants. There is no need to replicate these
is the chip DTSI since the value cannot be changes. Fix the syntax
of the cell size constant to match the naming convention used
thoughout DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update the Microchip XEC pinmux driver to use system I/O
routine for read/write of registers instead of direct use
of volatile and CMSIS defines. Add GPIO port number to
bindings instead of using hard coded value from chip headers.
Modify SoC DTSI pinmux syntax, requires "pinmux: pinumx {..."
or the DT macros will not work. Since pinmux is used by MEC152x
we update its chip pinmux DT.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In the eeprom read operation, when rambuf was available
mutex was not unlocked after the read. Consequence of that is
that device was blocked after that read for incoming operations.
This commit fixes the issue
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
